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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "We haven't seen a whole lot of fixes for the first two weeks since the merge window, but here is the batch that we have at the moment. Nothing sticks out as particularly bad or scary, it's mostly a handful of smaller fixes to several platforms. The Uniphier reset controller changes could probably have been delayed to 4.10, but they're not scary and just plumbing up driver changes that went in during the merge window. We're also adding another maintainer to Marvell Berlin platforms, to help out when Sebastian is too busy. Yay teamwork!" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: imx: mach-imx6q: Fix the PHY ID mask for AR8031 ARM: dts: vf610: fix IRQ flag of global timer ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path ARM: imx: gpc: Initialize all power domains arm64: dts: Updated NAND DT properties for NS2 SVK arm64: dts: uniphier: change MIO node to SD control node ARM: dts: uniphier: change MIO node to SD control node reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER arm64: dts: Add timer erratum property for LS2080A and LS1043A arm64: dts: rockchip: remove the abuse of keep-power-in-suspend ARM: multi_v7_defconfig: Enable Intel e1000e driver MAINTAINERS: add myself as Marvell berlin SoC maintainer bus: qcom-ebi2: depend on ARCH_QCOM or COMPILE_TEST ARM: dts: fix the SD card on the Snowball arm64: dts: rockchip: remove always-on and boot-on from vcc_sd arm64: dts: marvell: fix clocksource for CP110 master SPI0 ARM: mvebu: Select corediv clk for all mvebu v7 SoC
2 parents 2a29003 + b70e8be commit 2674235

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‎Documentation/devicetree/bindings/reset/uniphier-reset.txt

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -6,56 +6,56 @@ System reset
66

77
Required properties:
88
- compatible: should be one of the following:
9-
"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
10-
"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
11-
"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
12-
"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
13-
"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
14-
"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
15-
"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
16-
"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
9+
"socionext,uniphier-sld3-reset" - for sLD3 SoC.
10+
"socionext,uniphier-ld4-reset" - for LD4 SoC.
11+
"socionext,uniphier-pro4-reset" - for Pro4 SoC.
12+
"socionext,uniphier-sld8-reset" - for sLD8 SoC.
13+
"socionext,uniphier-pro5-reset" - for Pro5 SoC.
14+
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
15+
"socionext,uniphier-ld11-reset" - for LD11 SoC.
16+
"socionext,uniphier-ld20-reset" - for LD20 SoC.
1717
- #reset-cells: should be 1.
1818

1919
Example:
2020

2121
sysctrl@61840000 {
22-
compatible = "socionext,uniphier-ld20-sysctrl",
22+
compatible = "socionext,uniphier-ld11-sysctrl",
2323
"simple-mfd", "syscon";
2424
reg = <0x61840000 0x4000>;
2525

2626
reset {
27-
compatible = "socionext,uniphier-ld20-reset";
27+
compatible = "socionext,uniphier-ld11-reset";
2828
#reset-cells = <1>;
2929
};
3030

3131
other nodes ...
3232
};
3333

3434

35-
Media I/O (MIO) reset
36-
---------------------
35+
Media I/O (MIO) reset, SD reset
36+
-------------------------------
3737

3838
Required properties:
3939
- compatible: should be one of the following:
40-
"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
41-
"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
42-
"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
43-
"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
44-
"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
45-
"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
46-
"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
47-
"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
40+
"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
41+
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
42+
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
43+
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
44+
"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
45+
"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
46+
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
47+
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
4848
- #reset-cells: should be 1.
4949

5050
Example:
5151

5252
mioctrl@59810000 {
53-
compatible = "socionext,uniphier-ld20-mioctrl",
53+
compatible = "socionext,uniphier-ld11-mioctrl",
5454
"simple-mfd", "syscon";
5555
reg = <0x59810000 0x800>;
5656

5757
reset {
58-
compatible = "socionext,uniphier-ld20-mio-reset";
58+
compatible = "socionext,uniphier-ld11-mio-reset";
5959
#reset-cells = <1>;
6060
};
6161

@@ -68,24 +68,24 @@ Peripheral reset
6868

6969
Required properties:
7070
- compatible: should be one of the following:
71-
"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
72-
"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
73-
"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
74-
"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
75-
"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
76-
"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
77-
"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
71+
"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
72+
"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
73+
"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
74+
"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
75+
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
76+
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
77+
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
7878
- #reset-cells: should be 1.
7979

8080
Example:
8181

8282
perictrl@59820000 {
83-
compatible = "socionext,uniphier-ld20-perictrl",
83+
compatible = "socionext,uniphier-ld11-perictrl",
8484
"simple-mfd", "syscon";
8585
reg = <0x59820000 0x200>;
8686

8787
reset {
88-
compatible = "socionext,uniphier-ld20-peri-reset";
88+
compatible = "socionext,uniphier-ld11-peri-reset";
8989
#reset-cells = <1>;
9090
};
9191

‎MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1442,6 +1442,7 @@ F: drivers/cpufreq/mvebu-cpufreq.c
14421442
F: arch/arm/configs/mvebu_*_defconfig
14431443

14441444
ARM/Marvell Berlin SoC support
1445+
M: Jisheng Zhang <[email protected]>
14451446
M: Sebastian Hesselbarth <[email protected]>
14461447
L: [email protected] (moderated for non-subscribers)
14471448
S: Maintained

‎arch/arm/boot/dts/ste-snowball.dts

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -239,14 +239,25 @@
239239
arm,primecell-periphid = <0x10480180>;
240240
max-frequency = <100000000>;
241241
bus-width = <4>;
242+
cap-sd-highspeed;
242243
cap-mmc-highspeed;
244+
sd-uhs-sdr12;
245+
sd-uhs-sdr25;
246+
/* All direction control is used */
247+
st,sig-dir-cmd;
248+
st,sig-dir-dat0;
249+
st,sig-dir-dat2;
250+
st,sig-dir-dat31;
251+
st,sig-pin-fbclk;
252+
full-pwr-cycle;
243253
vmmc-supply = <&ab8500_ldo_aux3_reg>;
244254
vqmmc-supply = <&vmmci>;
245255
pinctrl-names = "default", "sleep";
246256
pinctrl-0 = <&sdi0_default_mode>;
247257
pinctrl-1 = <&sdi0_sleep_mode>;
248258

249-
cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218
259+
/* GPIO218 MMC_CD */
260+
cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>;
250261

251262
status = "okay";
252263
};
@@ -549,7 +560,7 @@
549560
/* VMMCI level-shifter enable */
550561
snowball_cfg3 {
551562
pins = "GPIO217_AH12";
552-
ste,config = <&gpio_out_lo>;
563+
ste,config = <&gpio_out_hi>;
553564
};
554565
/* VMMCI level-shifter voltage select */
555566
snowball_cfg4 {

‎arch/arm/boot/dts/uniphier-pro5.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -184,11 +184,11 @@
184184
};
185185

186186
&mio_clk {
187-
compatible = "socionext,uniphier-pro5-mio-clock";
187+
compatible = "socionext,uniphier-pro5-sd-clock";
188188
};
189189

190190
&mio_rst {
191-
compatible = "socionext,uniphier-pro5-mio-reset";
191+
compatible = "socionext,uniphier-pro5-sd-reset";
192192
};
193193

194194
&peri_clk {

‎arch/arm/boot/dts/uniphier-pxs2.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -197,11 +197,11 @@
197197
};
198198

199199
&mio_clk {
200-
compatible = "socionext,uniphier-pxs2-mio-clock";
200+
compatible = "socionext,uniphier-pxs2-sd-clock";
201201
};
202202

203203
&mio_rst {
204-
compatible = "socionext,uniphier-pxs2-mio-reset";
204+
compatible = "socionext,uniphier-pxs2-sd-reset";
205205
};
206206

207207
&peri_clk {

‎arch/arm/boot/dts/vf500.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@
7070
global_timer: timer@40002200 {
7171
compatible = "arm,cortex-a9-global-timer";
7272
reg = <0x40002200 0x20>;
73-
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
73+
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
7474
interrupt-parent = <&intc>;
7575
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
7676
};

‎arch/arm/configs/multi_v7_defconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -850,6 +850,7 @@ CONFIG_PWM_SUN4I=y
850850
CONFIG_PWM_TEGRA=y
851851
CONFIG_PWM_VT8500=y
852852
CONFIG_PHY_HIX5HD2_SATA=y
853+
CONFIG_E1000E=y
853854
CONFIG_PWM_STI=y
854855
CONFIG_PWM_BCM2835=y
855856
CONFIG_PWM_BRCMSTB=m

‎arch/arm/mach-imx/gpc.c

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,7 @@ static struct genpd_onecell_data imx_gpc_onecell_data = {
408408
static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
409409
{
410410
struct clk *clk;
411-
int i;
411+
int i, ret;
412412

413413
imx6q_pu_domain.reg = pu_reg;
414414

@@ -430,13 +430,22 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
430430
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
431431
return 0;
432432

433-
pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
434-
return of_genpd_add_provider_onecell(dev->of_node,
433+
for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
434+
pm_genpd_init(imx_gpc_domains[i], NULL, false);
435+
436+
ret = of_genpd_add_provider_onecell(dev->of_node,
435437
&imx_gpc_onecell_data);
438+
if (ret)
439+
goto power_off;
440+
441+
return 0;
436442

443+
power_off:
444+
imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
437445
clk_err:
438446
while (i--)
439447
clk_put(imx6q_pu_domain.clk[i]);
448+
imx6q_pu_domain.reg = NULL;
440449
return -EINVAL;
441450
}
442451

‎arch/arm/mach-imx/mach-imx6q.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ static void __init imx6q_enet_phy_init(void)
173173
ksz9021rn_phy_fixup);
174174
phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
175175
ksz9031rn_phy_fixup);
176-
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
176+
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
177177
ar8031_phy_fixup);
178178
phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
179179
ar8035_phy_fixup);

‎arch/arm/mach-mvebu/Kconfig

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ config MACH_MVEBU_V7
2323
select CACHE_L2X0
2424
select ARM_CPU_SUSPEND
2525
select MACH_MVEBU_ANY
26+
select MVEBU_CLK_COREDIV
2627

2728
config MACH_ARMADA_370
2829
bool "Marvell Armada 370 boards"
@@ -32,7 +33,6 @@ config MACH_ARMADA_370
3233
select CPU_PJ4B
3334
select MACH_MVEBU_V7
3435
select PINCTRL_ARMADA_370
35-
select MVEBU_CLK_COREDIV
3636
help
3737
Say 'Y' here if you want your kernel to support boards based
3838
on the Marvell Armada 370 SoC with device tree.
@@ -50,7 +50,6 @@ config MACH_ARMADA_375
5050
select HAVE_SMP
5151
select MACH_MVEBU_V7
5252
select PINCTRL_ARMADA_375
53-
select MVEBU_CLK_COREDIV
5453
help
5554
Say 'Y' here if you want your kernel to support boards based
5655
on the Marvell Armada 375 SoC with device tree.
@@ -68,7 +67,6 @@ config MACH_ARMADA_38X
6867
select HAVE_SMP
6968
select MACH_MVEBU_V7
7069
select PINCTRL_ARMADA_38X
71-
select MVEBU_CLK_COREDIV
7270
help
7371
Say 'Y' here if you want your kernel to support boards based
7472
on the Marvell Armada 380/385 SoC with device tree.

‎arch/arm/mach-uniphier/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
config ARCH_UNIPHIER
22
bool "Socionext UniPhier SoCs"
33
depends on ARCH_MULTI_V7
4+
select ARCH_HAS_RESET_CONTROLLER
45
select ARM_AMBA
56
select ARM_GLOBAL_TIMER
67
select ARM_GIC

‎arch/arm64/Kconfig.platforms

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,7 @@ config ARCH_THUNDER
190190

191191
config ARCH_UNIPHIER
192192
bool "Socionext UniPhier SoC Family"
193+
select ARCH_HAS_RESET_CONTROLLER
193194
select PINCTRL
194195
help
195196
This enables support for Socionext UniPhier SoC family.

‎arch/arm64/boot/dts/broadcom/ns2-svk.dts

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,8 @@
164164
nand-ecc-mode = "hw";
165165
nand-ecc-strength = <8>;
166166
nand-ecc-step-size = <512>;
167+
nand-bus-width = <16>;
168+
brcm,nand-oob-sector-size = <16>;
167169
#address-cells = <1>;
168170
#size-cells = <1>;
169171
};

‎arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@
123123
<1 14 0xf08>, /* Physical Non-Secure PPI */
124124
<1 11 0xf08>, /* Virtual PPI */
125125
<1 10 0xf08>; /* Hypervisor PPI */
126+
fsl,erratum-a008585;
126127
};
127128

128129
pmu {

‎arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,7 @@
195195
<1 14 4>, /* Physical Non-Secure PPI, active-low */
196196
<1 11 4>, /* Virtual PPI, active-low */
197197
<1 10 4>; /* Hypervisor PPI, active-low */
198+
fsl,erratum-a008585;
198199
};
199200

200201
pmu {

‎arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
#address-cells = <0x1>;
132132
#size-cells = <0x0>;
133133
cell-index = <1>;
134-
clocks = <&cpm_syscon0 0 3>;
134+
clocks = <&cpm_syscon0 1 21>;
135135
status = "disabled";
136136
};
137137

‎arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,6 @@
116116
cap-mmc-highspeed;
117117
clock-frequency = <150000000>;
118118
disable-wp;
119-
keep-power-in-suspend;
120119
non-removable;
121120
num-slots = <1>;
122121
vmmc-supply = <&vcc_io>;
@@ -258,8 +257,6 @@
258257
};
259258

260259
vcc_sd: SWITCH_REG1 {
261-
regulator-always-on;
262-
regulator-boot-on;
263260
regulator-name = "vcc_sd";
264261
};
265262

‎arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -152,8 +152,6 @@
152152
gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
153153
regulator-min-microvolt = <1800000>;
154154
regulator-max-microvolt = <3300000>;
155-
regulator-always-on;
156-
regulator-boot-on;
157155
vin-supply = <&vcc_io>;
158156
};
159157

@@ -201,7 +199,6 @@
201199
bus-width = <8>;
202200
cap-mmc-highspeed;
203201
disable-wp;
204-
keep-power-in-suspend;
205202
mmc-pwrseq = <&emmc_pwrseq>;
206203
mmc-hs200-1_2v;
207204
mmc-hs200-1_8v;
@@ -350,7 +347,6 @@
350347
clock-freq-min-max = <400000 50000000>;
351348
cap-sd-highspeed;
352349
card-detect-delay = <200>;
353-
keep-power-in-suspend;
354350
num-slots = <1>;
355351
pinctrl-names = "default";
356352
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;

‎arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -257,18 +257,18 @@
257257
reg = <0x59801000 0x400>;
258258
};
259259

260-
mioctrl@59810000 {
261-
compatible = "socionext,uniphier-mioctrl",
260+
sdctrl@59810000 {
261+
compatible = "socionext,uniphier-ld20-sdctrl",
262262
"simple-mfd", "syscon";
263263
reg = <0x59810000 0x800>;
264264

265-
mio_clk: clock {
266-
compatible = "socionext,uniphier-ld20-mio-clock";
265+
sd_clk: clock {
266+
compatible = "socionext,uniphier-ld20-sd-clock";
267267
#clock-cells = <1>;
268268
};
269269

270-
mio_rst: reset {
271-
compatible = "socionext,uniphier-ld20-mio-reset";
270+
sd_rst: reset {
271+
compatible = "socionext,uniphier-ld20-sd-reset";
272272
#reset-cells = <1>;
273273
};
274274
};

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