Skip to content

Commit 2d2e1dd

Browse files
lunndavem330
lunn
authored and
davem330
committed
net: dsa: mv88e6xxx: Cache the port cmode
The ports CMODE indicates the type of link between the MAC and the PHY. It is used often in the SERDES code. Rather than read it each time, cache its value. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
1 parent f8236a0 commit 2d2e1dd

File tree

5 files changed

+57
-47
lines changed

5 files changed

+57
-47
lines changed

‎drivers/net/dsa/mv88e6xxx/chip.c

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2381,6 +2381,7 @@ static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
23812381
static int mv88e6xxx_setup(struct dsa_switch *ds)
23822382
{
23832383
struct mv88e6xxx_chip *chip = ds->priv;
2384+
u8 cmode;
23842385
int err;
23852386
int i;
23862387

@@ -2389,6 +2390,17 @@ static int mv88e6xxx_setup(struct dsa_switch *ds)
23892390

23902391
mutex_lock(&chip->reg_lock);
23912392

2393+
/* Cache the cmode of each port. */
2394+
for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2395+
if (chip->info->ops->port_get_cmode) {
2396+
err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2397+
if (err)
2398+
return err;
2399+
2400+
chip->ports[i].cmode = cmode;
2401+
}
2402+
}
2403+
23922404
/* Setup Switch Port Registers */
23932405
for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
23942406
if (dsa_is_unused_port(ds, i))
@@ -2697,6 +2709,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
26972709
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
26982710
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
26992711
.port_link_state = mv88e6352_port_link_state,
2712+
.port_get_cmode = mv88e6185_port_get_cmode,
27002713
.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
27012714
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
27022715
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2730,6 +2743,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
27302743
.port_set_egress_floods = mv88e6185_port_set_egress_floods,
27312744
.port_set_upstream_port = mv88e6095_port_set_upstream_port,
27322745
.port_link_state = mv88e6185_port_link_state,
2746+
.port_get_cmode = mv88e6185_port_get_cmode,
27332747
.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
27342748
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
27352749
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2765,6 +2779,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
27652779
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
27662780
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
27672781
.port_link_state = mv88e6352_port_link_state,
2782+
.port_get_cmode = mv88e6185_port_get_cmode,
27682783
.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
27692784
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
27702785
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2798,6 +2813,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
27982813
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
27992814
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
28002815
.port_link_state = mv88e6352_port_link_state,
2816+
.port_get_cmode = mv88e6185_port_get_cmode,
28012817
.stats_snapshot = mv88e6320_g1_stats_snapshot,
28022818
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
28032819
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2834,6 +2850,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
28342850
.port_pause_limit = mv88e6097_port_pause_limit,
28352851
.port_set_pause = mv88e6185_port_set_pause,
28362852
.port_link_state = mv88e6352_port_link_state,
2853+
.port_get_cmode = mv88e6185_port_get_cmode,
28372854
.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
28382855
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
28392856
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2876,6 +2893,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
28762893
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
28772894
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
28782895
.port_link_state = mv88e6352_port_link_state,
2896+
.port_get_cmode = mv88e6352_port_get_cmode,
28792897
.stats_snapshot = mv88e6390_g1_stats_snapshot,
28802898
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
28812899
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -2915,6 +2933,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
29152933
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
29162934
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
29172935
.port_link_state = mv88e6352_port_link_state,
2936+
.port_get_cmode = mv88e6185_port_get_cmode,
29182937
.stats_snapshot = mv88e6320_g1_stats_snapshot,
29192938
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
29202939
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2947,6 +2966,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
29472966
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
29482967
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
29492968
.port_link_state = mv88e6352_port_link_state,
2969+
.port_get_cmode = mv88e6185_port_get_cmode,
29502970
.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
29512971
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
29522972
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2987,6 +3007,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
29873007
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
29883008
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
29893009
.port_link_state = mv88e6352_port_link_state,
3010+
.port_get_cmode = mv88e6352_port_get_cmode,
29903011
.stats_snapshot = mv88e6320_g1_stats_snapshot,
29913012
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
29923013
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3027,6 +3048,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
30273048
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
30283049
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
30293050
.port_link_state = mv88e6352_port_link_state,
3051+
.port_get_cmode = mv88e6352_port_get_cmode,
30303052
.stats_snapshot = mv88e6320_g1_stats_snapshot,
30313053
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
30323054
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3068,6 +3090,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
30683090
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
30693091
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
30703092
.port_link_state = mv88e6352_port_link_state,
3093+
.port_get_cmode = mv88e6352_port_get_cmode,
30713094
.stats_snapshot = mv88e6320_g1_stats_snapshot,
30723095
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
30733096
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3108,6 +3131,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
31083131
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
31093132
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
31103133
.port_link_state = mv88e6352_port_link_state,
3134+
.port_get_cmode = mv88e6352_port_get_cmode,
31113135
.stats_snapshot = mv88e6320_g1_stats_snapshot,
31123136
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
31133137
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3143,6 +3167,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
31433167
.port_set_upstream_port = mv88e6095_port_set_upstream_port,
31443168
.port_set_pause = mv88e6185_port_set_pause,
31453169
.port_link_state = mv88e6185_port_link_state,
3170+
.port_get_cmode = mv88e6185_port_get_cmode,
31463171
.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
31473172
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
31483173
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3181,6 +3206,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
31813206
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
31823207
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
31833208
.port_link_state = mv88e6352_port_link_state,
3209+
.port_get_cmode = mv88e6352_port_get_cmode,
31843210
.stats_snapshot = mv88e6390_g1_stats_snapshot,
31853211
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
31863212
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3220,6 +3246,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
32203246
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
32213247
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
32223248
.port_link_state = mv88e6352_port_link_state,
3249+
.port_get_cmode = mv88e6352_port_get_cmode,
32233250
.stats_snapshot = mv88e6390_g1_stats_snapshot,
32243251
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
32253252
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3259,6 +3286,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
32593286
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
32603287
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
32613288
.port_link_state = mv88e6352_port_link_state,
3289+
.port_get_cmode = mv88e6352_port_get_cmode,
32623290
.stats_snapshot = mv88e6390_g1_stats_snapshot,
32633291
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
32643292
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3303,6 +3331,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
33033331
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
33043332
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
33053333
.port_link_state = mv88e6352_port_link_state,
3334+
.port_get_cmode = mv88e6352_port_get_cmode,
33063335
.stats_snapshot = mv88e6320_g1_stats_snapshot,
33073336
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
33083337
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3345,6 +3374,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
33453374
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
33463375
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
33473376
.port_link_state = mv88e6352_port_link_state,
3377+
.port_get_cmode = mv88e6352_port_get_cmode,
33483378
.stats_snapshot = mv88e6390_g1_stats_snapshot,
33493379
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
33503380
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3389,6 +3419,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
33893419
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
33903420
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
33913421
.port_link_state = mv88e6352_port_link_state,
3422+
.port_get_cmode = mv88e6352_port_get_cmode,
33923423
.stats_snapshot = mv88e6320_g1_stats_snapshot,
33933424
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
33943425
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3430,6 +3461,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
34303461
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
34313462
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
34323463
.port_link_state = mv88e6352_port_link_state,
3464+
.port_get_cmode = mv88e6352_port_get_cmode,
34333465
.stats_snapshot = mv88e6320_g1_stats_snapshot,
34343466
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
34353467
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3470,6 +3502,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
34703502
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
34713503
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
34723504
.port_link_state = mv88e6352_port_link_state,
3505+
.port_get_cmode = mv88e6352_port_get_cmode,
34733506
.stats_snapshot = mv88e6390_g1_stats_snapshot,
34743507
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
34753508
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3512,6 +3545,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
35123545
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
35133546
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
35143547
.port_link_state = mv88e6352_port_link_state,
3548+
.port_get_cmode = mv88e6352_port_get_cmode,
35153549
.stats_snapshot = mv88e6320_g1_stats_snapshot,
35163550
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
35173551
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3550,6 +3584,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
35503584
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
35513585
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
35523586
.port_link_state = mv88e6352_port_link_state,
3587+
.port_get_cmode = mv88e6352_port_get_cmode,
35533588
.stats_snapshot = mv88e6320_g1_stats_snapshot,
35543589
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
35553590
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3592,6 +3627,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
35923627
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
35933628
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
35943629
.port_link_state = mv88e6352_port_link_state,
3630+
.port_get_cmode = mv88e6352_port_get_cmode,
35953631
.stats_snapshot = mv88e6320_g1_stats_snapshot,
35963632
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
35973633
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3639,6 +3675,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
36393675
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
36403676
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
36413677
.port_link_state = mv88e6352_port_link_state,
3678+
.port_get_cmode = mv88e6352_port_get_cmode,
36423679
.stats_snapshot = mv88e6390_g1_stats_snapshot,
36433680
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
36443681
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3683,6 +3720,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
36833720
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
36843721
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
36853722
.port_link_state = mv88e6352_port_link_state,
3723+
.port_get_cmode = mv88e6352_port_get_cmode,
36863724
.stats_snapshot = mv88e6390_g1_stats_snapshot,
36873725
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
36883726
.stats_get_sset_count = mv88e6320_stats_get_sset_count,

‎drivers/net/dsa/mv88e6xxx/chip.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,7 @@ struct mv88e6xxx_port {
197197
u64 atu_full_violation;
198198
u64 vtu_member_violation;
199199
u64 vtu_miss_violation;
200+
u8 cmode;
200201
};
201202

202203
struct mv88e6xxx_chip {
@@ -390,6 +391,7 @@ struct mv88e6xxx_ops {
390391
*/
391392
int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
392393
phy_interface_t mode);
394+
int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
393395

394396
/* Some devices have a per port register indicating what is
395397
* the upstream port this port should forward to.

‎drivers/net/dsa/mv88e6xxx/port.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -385,11 +385,12 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
385385
return err;
386386
}
387387

388+
chip->ports[port].cmode = cmode;
389+
388390
return 0;
389391
}
390392

391-
/* mv88e6185 only has 3 bits for CMODE */
392-
static int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port)
393+
int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
393394
{
394395
int err;
395396
u16 reg;
@@ -398,10 +399,12 @@ static int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port)
398399
if (err)
399400
return err;
400401

401-
return reg & MV88E6185_PORT_STS_CMODE_MASK;
402+
*cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
403+
404+
return 0;
402405
}
403406

404-
int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
407+
int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
405408
{
406409
int err;
407410
u16 reg;
@@ -457,10 +460,7 @@ int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
457460
struct phylink_link_state *state)
458461
{
459462
if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
460-
int cmode = mv88e6185_port_get_cmode(chip, port);
461-
462-
if (cmode < 0)
463-
return cmode;
463+
u8 cmode = chip->ports[port].cmode;
464464

465465
/* When a port is in "Cross-chip serdes" mode, it uses
466466
* 1000Base-X full duplex mode, but there is no automatic

‎drivers/net/dsa/mv88e6xxx/port.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -311,7 +311,8 @@ int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
311311
u8 out);
312312
int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
313313
phy_interface_t mode);
314-
int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
314+
int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
315+
int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
315316
int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
316317
struct phylink_link_state *state);
317318
int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,

‎drivers/net/dsa/mv88e6xxx/serdes.c

Lines changed: 7 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -73,14 +73,7 @@ static int mv88e6352_serdes_power_set(struct mv88e6xxx_chip *chip, bool on)
7373

7474
static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port)
7575
{
76-
u8 cmode;
77-
int err;
78-
79-
err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
80-
if (err) {
81-
dev_err(chip->dev, "failed to read cmode\n");
82-
return false;
83-
}
76+
u8 cmode = chip->ports[port].cmode;
8477

8578
if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASE_X) ||
8679
(cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X) ||
@@ -195,12 +188,7 @@ int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
195188
*/
196189
static int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
197190
{
198-
u8 cmode;
199-
int err;
200-
201-
err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
202-
if (err)
203-
return err;
191+
u8 cmode = chip->ports[port].cmode;
204192

205193
switch (port) {
206194
case 9:
@@ -227,19 +215,10 @@ static int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
227215
static int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
228216
{
229217
u8 cmode_port9, cmode_port10, cmode_port;
230-
int err;
231218

232-
err = mv88e6xxx_port_get_cmode(chip, 9, &cmode_port9);
233-
if (err)
234-
return err;
235-
236-
err = mv88e6xxx_port_get_cmode(chip, 10, &cmode_port10);
237-
if (err)
238-
return err;
239-
240-
err = mv88e6xxx_port_get_cmode(chip, port, &cmode_port);
241-
if (err)
242-
return err;
219+
cmode_port9 = chip->ports[9].cmode;
220+
cmode_port10 = chip->ports[10].cmode;
221+
cmode_port = chip->ports[port].cmode;
243222

244223
switch (port) {
245224
case 2:
@@ -365,12 +344,7 @@ static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, int lane,
365344
static int mv88e6390_serdes_power_lane(struct mv88e6xxx_chip *chip, int port,
366345
int lane, bool on)
367346
{
368-
u8 cmode;
369-
int err;
370-
371-
err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
372-
if (err)
373-
return err;
347+
u8 cmode = chip->ports[port].cmode;
374348

375349
switch (cmode) {
376350
case MV88E6XXX_PORT_STS_CMODE_SGMII:
@@ -427,16 +401,11 @@ int mv88e6390x_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
427401

428402
int mv88e6341_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
429403
{
430-
int err;
431-
u8 cmode;
404+
u8 cmode = chip->ports[port].cmode;
432405

433406
if (port != 5)
434407
return 0;
435408

436-
err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
437-
if (err)
438-
return err;
439-
440409
if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X ||
441410
cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
442411
cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)

0 commit comments

Comments
 (0)