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146 | 146 | /*
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147 | 147 | * Find irq with highest priority
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148 | 148 | */
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149 |
| - PTR_LA t1,cpu_mask_nr_tbl |
| 149 | + # open coded PTR_LA t1, cpu_mask_nr_tbl |
| 150 | +#if (_MIPS_SZPTR == 32) |
| 151 | + # open coded la t1, cpu_mask_nr_tbl |
| 152 | + lui t1, %hi(cpu_mask_nr_tbl) |
| 153 | + addiu t1, %lo(cpu_mask_nr_tbl) |
| 154 | + |
| 155 | +#endif |
| 156 | +#if (_MIPS_SZPTR == 64) |
| 157 | + # open coded dla t1, cpu_mask_nr_tbl |
| 158 | + .set push |
| 159 | + .set noat |
| 160 | + lui t1, %highest(cpu_mask_nr_tbl) |
| 161 | + lui AT, %hi(cpu_mask_nr_tbl) |
| 162 | + daddiu t1, t1, %higher(cpu_mask_nr_tbl) |
| 163 | + daddiu AT, AT, %lo(cpu_mask_nr_tbl) |
| 164 | + dsll t1, 32 |
| 165 | + daddu t1, t1, AT |
| 166 | + .set pop |
| 167 | +#endif |
150 | 168 | 1: lw t2,(t1)
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151 | 169 | nop
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152 | 170 | and t2,t0
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195 | 213 | /*
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196 | 214 | * Find irq with highest priority
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197 | 215 | */
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198 |
| - PTR_LA t1,asic_mask_nr_tbl |
| 216 | + # open coded PTR_LA t1,asic_mask_nr_tbl |
| 217 | +#if (_MIPS_SZPTR == 32) |
| 218 | + # open coded la t1, asic_mask_nr_tbl |
| 219 | + lui t1, %hi(asic_mask_nr_tbl) |
| 220 | + addiu t1, %lo(asic_mask_nr_tbl) |
| 221 | + |
| 222 | +#endif |
| 223 | +#if (_MIPS_SZPTR == 64) |
| 224 | + # open coded dla t1, asic_mask_nr_tbl |
| 225 | + .set push |
| 226 | + .set noat |
| 227 | + lui t1, %highest(asic_mask_nr_tbl) |
| 228 | + lui AT, %hi(asic_mask_nr_tbl) |
| 229 | + daddiu t1, t1, %higher(asic_mask_nr_tbl) |
| 230 | + daddiu AT, AT, %lo(asic_mask_nr_tbl) |
| 231 | + dsll t1, 32 |
| 232 | + daddu t1, t1, AT |
| 233 | + .set pop |
| 234 | +#endif |
199 | 235 | 2: lw t2,(t1)
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200 | 236 | nop
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201 | 237 | and t2,t0
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