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drm/i915/tgl: Add the Thunderbolt PLL divider values
The Thunderbolt PLL divider values on TGL differ from the ICL ones, update the PLL parameter calculation function accordingly. Bspec: 49204 v2: - Remove unused refclk config. (José) Cc: Jose Souza <[email protected]> Cc: Clinton A Taylor <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Mika Westerberg <[email protected]> Tested-by: Mika Westerberg <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Jose Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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drivers/gpu/drm/i915/display/intel_dpll_mgr.c

Lines changed: 40 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2520,6 +2520,18 @@ static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
25202520
.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
25212521
};
25222522

2523+
static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
2524+
.dco_integer = 0x54, .dco_fraction = 0x3000,
2525+
/* the following params are unused */
2526+
.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2527+
};
2528+
2529+
static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
2530+
.dco_integer = 0x43, .dco_fraction = 0x4000,
2531+
/* the following params are unused */
2532+
.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2533+
};
2534+
25232535
static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
25242536
struct skl_wrpll_params *pll_params)
25252537
{
@@ -2547,8 +2559,34 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
25472559
{
25482560
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
25492561

2550-
*pll_params = dev_priv->cdclk.hw.ref == 24000 ?
2551-
icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
2562+
if (INTEL_GEN(dev_priv) >= 12) {
2563+
switch (dev_priv->cdclk.hw.ref) {
2564+
default:
2565+
MISSING_CASE(dev_priv->cdclk.hw.ref);
2566+
/* fall-through */
2567+
case 19200:
2568+
case 38400:
2569+
*pll_params = tgl_tbt_pll_19_2MHz_values;
2570+
break;
2571+
case 24000:
2572+
*pll_params = tgl_tbt_pll_24MHz_values;
2573+
break;
2574+
}
2575+
} else {
2576+
switch (dev_priv->cdclk.hw.ref) {
2577+
default:
2578+
MISSING_CASE(dev_priv->cdclk.hw.ref);
2579+
/* fall-through */
2580+
case 19200:
2581+
case 38400:
2582+
*pll_params = icl_tbt_pll_19_2MHz_values;
2583+
break;
2584+
case 24000:
2585+
*pll_params = icl_tbt_pll_24MHz_values;
2586+
break;
2587+
}
2588+
}
2589+
25522590
return true;
25532591
}
25542592

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