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Michael Chandavem330
Michael Chan
authored and
davem330
committed
bnxt_en: Update firmware interface spec. to 1.10.0.47.
Firmware error recover is the major change in this spec. Signed-off-by: Michael Chan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

Lines changed: 177 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/* Broadcom NetXtreme-C/E network driver.
22
*
33
* Copyright (c) 2014-2016 Broadcom Corporation
4-
* Copyright (c) 2016-2018 Broadcom Limited
4+
* Copyright (c) 2016-2019 Broadcom Limited
55
*
66
* This program is free software; you can redistribute it and/or modify
77
* it under the terms of the GNU General Public License as published by
@@ -98,6 +98,7 @@ struct hwrm_short_input {
9898
struct cmd_nums {
9999
__le16 req_type;
100100
#define HWRM_VER_GET 0x0UL
101+
#define HWRM_ERROR_RECOVERY_QCFG 0xcUL
101102
#define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
102103
#define HWRM_FUNC_BUF_UNRGTR 0xeUL
103104
#define HWRM_FUNC_VF_CFG 0xfUL
@@ -221,6 +222,7 @@ struct cmd_nums {
221222
#define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
222223
#define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
223224
#define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
225+
#define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
224226
#define HWRM_CFA_VFR_ALLOC 0xfdUL
225227
#define HWRM_CFA_VFR_FREE 0xfeUL
226228
#define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
@@ -269,6 +271,7 @@ struct cmd_nums {
269271
#define HWRM_ENGINE_CKV_FLUSH 0x133UL
270272
#define HWRM_ENGINE_CKV_RNG_GET 0x134UL
271273
#define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
274+
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
272275
#define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
273276
#define HWRM_ENGINE_QG_QUERY 0x13dUL
274277
#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
@@ -296,6 +299,7 @@ struct cmd_nums {
296299
#define HWRM_ENGINE_NQ_ALLOC 0x162UL
297300
#define HWRM_ENGINE_NQ_FREE 0x163UL
298301
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
302+
#define HWRM_ENGINE_FUNC_QCFG 0x165UL
299303
#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
300304
#define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
301305
#define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
@@ -379,15 +383,15 @@ struct hwrm_err_output {
379383
};
380384
#define HWRM_NA_SIGNATURE ((__le32)(-1))
381385
#define HWRM_MAX_REQ_LEN 128
382-
#define HWRM_MAX_RESP_LEN 280
386+
#define HWRM_MAX_RESP_LEN 704
383387
#define HW_HASH_INDEX_SIZE 0x80
384388
#define HW_HASH_KEY_SIZE 40
385389
#define HWRM_RESP_VALID_KEY 1
386390
#define HWRM_VERSION_MAJOR 1
387391
#define HWRM_VERSION_MINOR 10
388392
#define HWRM_VERSION_UPDATE 0
389-
#define HWRM_VERSION_RSVD 35
390-
#define HWRM_VERSION_STR "1.10.0.35"
393+
#define HWRM_VERSION_RSVD 47
394+
#define HWRM_VERSION_STR "1.10.0.47"
391395

392396
/* hwrm_ver_get_input (size:192b/24B) */
393397
struct hwrm_ver_get_input {
@@ -580,6 +584,7 @@ struct hwrm_async_event_cmpl {
580584
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
581585
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
582586
#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
587+
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
583588
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
584589
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
585590
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
@@ -595,6 +600,9 @@ struct hwrm_async_event_cmpl {
595600
#define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
596601
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
597602
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
603+
#define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
604+
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
605+
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
598606
#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
599607
#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
600608
#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
@@ -724,6 +732,30 @@ struct hwrm_async_event_cmpl_reset_notify {
724732
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
725733
};
726734

735+
/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
736+
struct hwrm_async_event_cmpl_error_recovery {
737+
__le16 type;
738+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
739+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
740+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
741+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
742+
__le16 event_id;
743+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
744+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
745+
__le32 event_data2;
746+
u8 opaque_v;
747+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
748+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
749+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
750+
u8 timestamp_lo;
751+
__le16 timestamp_hi;
752+
__le32 event_data1;
753+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
754+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
755+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
756+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
757+
};
758+
727759
/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
728760
struct hwrm_async_event_cmpl_vf_cfg_change {
729761
__le16 type;
@@ -1014,6 +1046,7 @@ struct hwrm_func_qcaps_output {
10141046
#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
10151047
#define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
10161048
#define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1049+
#define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
10171050
u8 mac_address[6];
10181051
__le16 max_rsscos_ctx;
10191052
__le16 max_cmpl_rings;
@@ -1185,6 +1218,7 @@ struct hwrm_func_cfg_input {
11851218
#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
11861219
#define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
11871220
#define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
1221+
#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
11881222
__le32 enables;
11891223
#define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
11901224
#define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
@@ -1390,6 +1424,7 @@ struct hwrm_func_drv_rgtr_input {
13901424
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
13911425
#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
13921426
#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1427+
#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
13931428
__le32 enables;
13941429
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
13951430
#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
@@ -2024,6 +2059,89 @@ struct hwrm_func_backing_store_cfg_output {
20242059
u8 valid;
20252060
};
20262061

2062+
/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
2063+
struct hwrm_error_recovery_qcfg_input {
2064+
__le16 req_type;
2065+
__le16 cmpl_ring;
2066+
__le16 seq_id;
2067+
__le16 target_id;
2068+
__le64 resp_addr;
2069+
u8 unused_0[8];
2070+
};
2071+
2072+
/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
2073+
struct hwrm_error_recovery_qcfg_output {
2074+
__le16 error_code;
2075+
__le16 req_type;
2076+
__le16 seq_id;
2077+
__le16 resp_len;
2078+
__le32 flags;
2079+
#define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
2080+
#define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
2081+
__le32 driver_polling_freq;
2082+
__le32 master_func_wait_period;
2083+
__le32 normal_func_wait_period;
2084+
__le32 master_func_wait_period_after_reset;
2085+
__le32 max_bailout_time_after_reset;
2086+
__le32 fw_health_status_reg;
2087+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
2088+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
2089+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2090+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
2091+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
2092+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
2093+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
2094+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
2095+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
2096+
__le32 fw_heartbeat_reg;
2097+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
2098+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
2099+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2100+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
2101+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
2102+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
2103+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
2104+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
2105+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
2106+
__le32 fw_reset_cnt_reg;
2107+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
2108+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
2109+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2110+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
2111+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
2112+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
2113+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
2114+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
2115+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
2116+
__le32 reset_inprogress_reg;
2117+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
2118+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
2119+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2120+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
2121+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
2122+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
2123+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
2124+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
2125+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
2126+
__le32 reset_inprogress_reg_mask;
2127+
u8 unused_0[3];
2128+
u8 reg_array_cnt;
2129+
__le32 reset_reg[16];
2130+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
2131+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
2132+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2133+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
2134+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
2135+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
2136+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
2137+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
2138+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
2139+
__le32 reset_reg_val[16];
2140+
u8 delay_after_reset[16];
2141+
u8 unused_1[7];
2142+
u8 valid;
2143+
};
2144+
20272145
/* hwrm_func_drv_if_change_input (size:192b/24B) */
20282146
struct hwrm_func_drv_if_change_input {
20292147
__le16 req_type;
@@ -2955,6 +3073,7 @@ struct hwrm_port_phy_qcaps_output {
29553073
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
29563074
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
29573075
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
3076+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB 0x4000UL
29583077
__le16 supported_speeds_auto_mode;
29593078
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
29603079
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
@@ -2970,6 +3089,7 @@ struct hwrm_port_phy_qcaps_output {
29703089
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
29713090
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
29723091
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
3092+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB 0x4000UL
29733093
__le16 supported_speeds_eee_mode;
29743094
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
29753095
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
@@ -4919,6 +5039,35 @@ struct hwrm_ring_free_output {
49195039
u8 valid;
49205040
};
49215041

5042+
/* hwrm_ring_reset_input (size:192b/24B) */
5043+
struct hwrm_ring_reset_input {
5044+
__le16 req_type;
5045+
__le16 cmpl_ring;
5046+
__le16 seq_id;
5047+
__le16 target_id;
5048+
__le64 resp_addr;
5049+
u8 ring_type;
5050+
#define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
5051+
#define RING_RESET_REQ_RING_TYPE_TX 0x1UL
5052+
#define RING_RESET_REQ_RING_TYPE_RX 0x2UL
5053+
#define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5054+
#define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL
5055+
u8 unused_0;
5056+
__le16 ring_id;
5057+
u8 unused_1[4];
5058+
};
5059+
5060+
/* hwrm_ring_reset_output (size:128b/16B) */
5061+
struct hwrm_ring_reset_output {
5062+
__le16 error_code;
5063+
__le16 req_type;
5064+
__le16 seq_id;
5065+
__le16 resp_len;
5066+
u8 unused_0[4];
5067+
u8 consumer_idx[3];
5068+
u8 valid;
5069+
};
5070+
49225071
/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
49235072
struct hwrm_ring_aggint_qcaps_input {
49245073
__le16 req_type;
@@ -5446,19 +5595,21 @@ struct hwrm_cfa_encap_record_alloc_input {
54465595
__le64 resp_addr;
54475596
__le32 flags;
54485597
#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5598+
#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL
54495599
u8 encap_type;
5450-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
5451-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
5452-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
5453-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
5454-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
5455-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
5456-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
5457-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
5458-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
5459-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
5460-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
5461-
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE
5600+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
5601+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
5602+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
5603+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
5604+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
5605+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
5606+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
5607+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
5608+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
5609+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
5610+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
5611+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
5612+
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
54625613
u8 unused_0[3];
54635614
__le32 encap_data[20];
54645615
};
@@ -5506,6 +5657,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
55065657
#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
55075658
#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
55085659
#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
5660+
#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL
55095661
__le32 enables;
55105662
#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
55115663
#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
@@ -5627,7 +5779,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
56275779
#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
56285780
#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
56295781
#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
5630-
u8 unused_0[4];
5782+
__le32 flags;
5783+
#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
56315784
__le64 ntuple_filter_id;
56325785
__le32 new_dst_id;
56335786
__le32 new_mirror_vnic_id;
@@ -5892,13 +6045,15 @@ struct hwrm_cfa_flow_info_input {
58926045
__le64 ext_flow_handle;
58936046
};
58946047

5895-
/* hwrm_cfa_flow_info_output (size:448b/56B) */
6048+
/* hwrm_cfa_flow_info_output (size:5632b/704B) */
58966049
struct hwrm_cfa_flow_info_output {
58976050
__le16 error_code;
58986051
__le16 req_type;
58996052
__le16 seq_id;
59006053
__le16 resp_len;
59016054
u8 flags;
6055+
#define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL
6056+
#define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL
59026057
u8 profile;
59036058
__le16 src_fid;
59046059
__le16 dst_fid;
@@ -5910,7 +6065,10 @@ struct hwrm_cfa_flow_info_output {
59106065
__le16 flow_handle;
59116066
__le32 tunnel_handle;
59126067
__le16 flow_timer;
5913-
u8 unused_0[5];
6068+
u8 unused_0[6];
6069+
__le32 flow_key_data[130];
6070+
__le32 flow_action_info[30];
6071+
u8 unused_1[7];
59146072
u8 valid;
59156073
};
59166074

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