Skip to content

Commit 32c9262

Browse files
Harry Austenbebarino
Harry Austen
authored and
bebarino
committed
clk: clocking-wizard: move clock registration to separate function
Provide clear separation of dynamic reconfiguration logic, by moving its setup procedure to its own dedicated function. Signed-off-by: Harry Austen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
1 parent fc51bad commit 32c9262

File tree

1 file changed

+75
-68
lines changed

1 file changed

+75
-68
lines changed

‎drivers/clk/xilinx/clk-xlnx-clock-wizard.c

Lines changed: 75 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -962,80 +962,38 @@ static const struct versal_clk_data versal_data = {
962962
.is_versal = true,
963963
};
964964

965-
static int clk_wzrd_probe(struct platform_device *pdev)
965+
static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs)
966966
{
967967
const char *clkout_name, *clk_name, *clk_mul_name;
968+
struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
968969
u32 regl, regh, edge, regld, reghd, edged, div;
969-
struct device_node *np = pdev->dev.of_node;
970970
const struct versal_clk_data *data;
971-
struct clk_wzrd *clk_wzrd;
972971
unsigned long flags = 0;
972+
bool is_versal = false;
973973
void __iomem *ctrl_reg;
974974
u32 reg, reg_f, mult;
975-
bool is_versal = false;
976-
unsigned long rate;
977-
int nr_outputs;
978-
int i, ret;
979-
980-
ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
981-
if (ret || nr_outputs > WZRD_NUM_OUTPUTS)
982-
return -EINVAL;
983-
984-
clk_wzrd = devm_kzalloc(&pdev->dev, struct_size(clk_wzrd, clk_data.hws, nr_outputs),
985-
GFP_KERNEL);
986-
if (!clk_wzrd)
987-
return -ENOMEM;
988-
platform_set_drvdata(pdev, clk_wzrd);
989-
990-
clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
991-
if (IS_ERR(clk_wzrd->base))
992-
return PTR_ERR(clk_wzrd->base);
993-
994-
ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
995-
if (!ret) {
996-
if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
997-
dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
998-
clk_wzrd->speed_grade);
999-
clk_wzrd->speed_grade = 0;
1000-
}
1001-
}
1002-
1003-
clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
1004-
if (IS_ERR(clk_wzrd->clk_in1))
1005-
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
1006-
"clk_in1 not found\n");
975+
int i;
1007976

1008-
clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
1009-
if (IS_ERR(clk_wzrd->axi_clk))
1010-
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
1011-
"s_axi_aclk not found\n");
1012-
rate = clk_get_rate(clk_wzrd->axi_clk);
1013-
if (rate > WZRD_ACLK_MAX_FREQ) {
1014-
dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n",
1015-
rate);
1016-
return -EINVAL;
1017-
}
1018-
1019-
data = device_get_match_data(&pdev->dev);
977+
data = device_get_match_data(dev);
1020978
if (data)
1021979
is_versal = data->is_versal;
1022980

1023-
clkout_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_out0", dev_name(&pdev->dev));
981+
clkout_name = devm_kasprintf(dev, GFP_KERNEL, "%s_out0", dev_name(dev));
1024982
if (!clkout_name)
1025983
return -ENOMEM;
1026984

1027985
if (is_versal) {
1028986
if (nr_outputs == 1) {
1029987
clk_wzrd->clk_data.hws[0] = clk_wzrd_ver_register_divider
1030-
(&pdev->dev, clkout_name,
988+
(dev, clkout_name,
1031989
__clk_get_name(clk_wzrd->clk_in1), 0,
1032990
clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),
1033991
WZRD_CLKOUT_DIVIDE_SHIFT,
1034992
WZRD_CLKOUT_DIVIDE_WIDTH,
1035993
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
1036994
DIV_ALL, &clkwzrd_lock);
1037995

1038-
goto out;
996+
return 0;
1039997
}
1040998
/* register multiplier */
1041999
edge = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0)) &
@@ -1060,15 +1018,15 @@ static int clk_wzrd_probe(struct platform_device *pdev)
10601018
} else {
10611019
if (nr_outputs == 1) {
10621020
clk_wzrd->clk_data.hws[0] = clk_wzrd_register_divider
1063-
(&pdev->dev, clkout_name,
1021+
(dev, clkout_name,
10641022
__clk_get_name(clk_wzrd->clk_in1), 0,
10651023
clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),
10661024
WZRD_CLKOUT_DIVIDE_SHIFT,
10671025
WZRD_CLKOUT_DIVIDE_WIDTH,
10681026
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
10691027
DIV_ALL, &clkwzrd_lock);
10701028

1071-
goto out;
1029+
return 0;
10721030
}
10731031
reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0));
10741032
reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK;
@@ -1079,19 +1037,19 @@ static int clk_wzrd_probe(struct platform_device *pdev)
10791037
mult = (reg * 1000) + reg_f;
10801038
div = 1000;
10811039
}
1082-
clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
1040+
clk_name = devm_kasprintf(dev, GFP_KERNEL, "%s_mul", dev_name(dev));
10831041
if (!clk_name)
10841042
return -ENOMEM;
10851043
clk_wzrd->clks_internal[wzrd_clk_mul] = devm_clk_hw_register_fixed_factor
1086-
(&pdev->dev, clk_name,
1044+
(dev, clk_name,
10871045
__clk_get_name(clk_wzrd->clk_in1),
10881046
0, mult, div);
10891047
if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
1090-
dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
1048+
dev_err(dev, "unable to register fixed-factor clock\n");
10911049
return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
10921050
}
10931051

1094-
clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
1052+
clk_name = devm_kasprintf(dev, GFP_KERNEL, "%s_mul_div", dev_name(dev));
10951053
if (!clk_name)
10961054
return -ENOMEM;
10971055

@@ -1108,31 +1066,29 @@ static int clk_wzrd_probe(struct platform_device *pdev)
11081066

11091067
clk_mul_name = clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]);
11101068
clk_wzrd->clks_internal[wzrd_clk_mul_div] =
1111-
devm_clk_hw_register_fixed_factor(&pdev->dev, clk_name,
1112-
clk_mul_name, 0, 1, div);
1069+
devm_clk_hw_register_fixed_factor(dev, clk_name, clk_mul_name, 0, 1, div);
11131070
} else {
11141071
ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0);
11151072
clk_wzrd->clks_internal[wzrd_clk_mul_div] = devm_clk_hw_register_divider
1116-
(&pdev->dev, clk_name,
1073+
(dev, clk_name,
11171074
clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
11181075
flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
11191076
CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock);
11201077
}
11211078
if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
1122-
dev_err(&pdev->dev, "unable to register divider clock\n");
1079+
dev_err(dev, "unable to register divider clock\n");
11231080
return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
11241081
}
11251082

11261083
/* register div per output */
11271084
for (i = nr_outputs - 1; i >= 0 ; i--) {
1128-
clkout_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1129-
"%s_out%d", dev_name(&pdev->dev), i);
1085+
clkout_name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%d", dev_name(dev), i);
11301086
if (!clkout_name)
11311087
return -ENOMEM;
11321088

11331089
if (is_versal) {
11341090
clk_wzrd->clk_data.hws[i] = clk_wzrd_ver_register_divider
1135-
(&pdev->dev,
1091+
(dev,
11361092
clkout_name, clk_name, 0,
11371093
clk_wzrd->base,
11381094
(WZRD_CLK_CFG_REG(is_versal, 3) + i * 8),
@@ -1144,29 +1100,80 @@ static int clk_wzrd_probe(struct platform_device *pdev)
11441100
} else {
11451101
if (!i)
11461102
clk_wzrd->clk_data.hws[i] = clk_wzrd_register_divf
1147-
(&pdev->dev, clkout_name, clk_name, flags, clk_wzrd->base,
1103+
(dev, clkout_name, clk_name, flags, clk_wzrd->base,
11481104
(WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),
11491105
WZRD_CLKOUT_DIVIDE_SHIFT,
11501106
WZRD_CLKOUT_DIVIDE_WIDTH,
11511107
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
11521108
DIV_O, &clkwzrd_lock);
11531109
else
11541110
clk_wzrd->clk_data.hws[i] = clk_wzrd_register_divider
1155-
(&pdev->dev, clkout_name, clk_name, 0, clk_wzrd->base,
1111+
(dev, clkout_name, clk_name, 0, clk_wzrd->base,
11561112
(WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),
11571113
WZRD_CLKOUT_DIVIDE_SHIFT,
11581114
WZRD_CLKOUT_DIVIDE_WIDTH,
11591115
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
11601116
DIV_O, &clkwzrd_lock);
11611117
}
11621118
if (IS_ERR(clk_wzrd->clk_data.hws[i])) {
1163-
dev_err(&pdev->dev,
1164-
"unable to register divider clock\n");
1119+
dev_err(dev, "unable to register divider clock\n");
11651120
return PTR_ERR(clk_wzrd->clk_data.hws[i]);
11661121
}
11671122
}
11681123

1169-
out:
1124+
return 0;
1125+
}
1126+
1127+
static int clk_wzrd_probe(struct platform_device *pdev)
1128+
{
1129+
struct device_node *np = pdev->dev.of_node;
1130+
struct clk_wzrd *clk_wzrd;
1131+
unsigned long rate;
1132+
int nr_outputs;
1133+
int ret;
1134+
1135+
ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
1136+
if (ret || nr_outputs > WZRD_NUM_OUTPUTS)
1137+
return -EINVAL;
1138+
1139+
clk_wzrd = devm_kzalloc(&pdev->dev, struct_size(clk_wzrd, clk_data.hws, nr_outputs),
1140+
GFP_KERNEL);
1141+
if (!clk_wzrd)
1142+
return -ENOMEM;
1143+
platform_set_drvdata(pdev, clk_wzrd);
1144+
1145+
clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
1146+
if (IS_ERR(clk_wzrd->base))
1147+
return PTR_ERR(clk_wzrd->base);
1148+
1149+
ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
1150+
if (!ret) {
1151+
if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
1152+
dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
1153+
clk_wzrd->speed_grade);
1154+
clk_wzrd->speed_grade = 0;
1155+
}
1156+
}
1157+
1158+
clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
1159+
if (IS_ERR(clk_wzrd->clk_in1))
1160+
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
1161+
"clk_in1 not found\n");
1162+
1163+
clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
1164+
if (IS_ERR(clk_wzrd->axi_clk))
1165+
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
1166+
"s_axi_aclk not found\n");
1167+
rate = clk_get_rate(clk_wzrd->axi_clk);
1168+
if (rate > WZRD_ACLK_MAX_FREQ) {
1169+
dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", rate);
1170+
return -EINVAL;
1171+
}
1172+
1173+
ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs);
1174+
if (ret)
1175+
return ret;
1176+
11701177
clk_wzrd->clk_data.num = nr_outputs;
11711178
ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, &clk_wzrd->clk_data);
11721179
if (ret) {

0 commit comments

Comments
 (0)