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Florian FainelliJeff Garzik
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r6040: use definitions for magic values in descriptor status
Define all the descriptor status the MAC can set. Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: Jeff Garzik <[email protected]>
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-11
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-11
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drivers/net/r6040.c

Lines changed: 26 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,21 @@
138138
#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139139
#define MCAST_MAX 4 /* Max number multicast addresses to filter */
140140

141+
/* Descriptor status */
142+
#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
143+
#define DSC_RX_OK 0x4000 /* RX was successful */
144+
#define DSC_RX_ERR 0x0800 /* RX PHY error */
145+
#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
146+
#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
147+
#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
148+
#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
149+
#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
150+
#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
151+
#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
152+
#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
153+
#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
154+
#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
155+
141156
/* PHY settings */
142157
#define ICPLUS_PHY_ID 0x0243
143158

@@ -324,7 +339,7 @@ static int r6040_alloc_rxbufs(struct net_device *dev)
324339
desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
325340
desc->skb_ptr->data,
326341
MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
327-
desc->status = 0x8000;
342+
desc->status = DSC_OWNER_MAC;
328343
desc = desc->vndescp;
329344
} while (desc != lp->rx_ring);
330345

@@ -541,25 +556,25 @@ static int r6040_rx(struct net_device *dev, int limit)
541556
u16 err;
542557

543558
/* Limit not reached and the descriptor belongs to the CPU */
544-
while (count < limit && !(descptr->status & 0x8000)) {
559+
while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
545560
/* Read the descriptor status */
546561
err = descptr->status;
547562
/* Global error status set */
548-
if (err & 0x0800) {
563+
if (err & DSC_RX_ERR) {
549564
/* RX dribble */
550-
if (err & 0x0400)
565+
if (err & DSC_RX_ERR_DRI)
551566
dev->stats.rx_frame_errors++;
552567
/* Buffer lenght exceeded */
553-
if (err & 0x0200)
568+
if (err & DSC_RX_ERR_BUF)
554569
dev->stats.rx_length_errors++;
555570
/* Packet too long */
556-
if (err & 0x0100)
571+
if (err & DSC_RX_ERR_LONG)
557572
dev->stats.rx_length_errors++;
558573
/* Packet < 64 bytes */
559-
if (err & 0x0080)
574+
if (err & DSC_RX_ERR_RUNT)
560575
dev->stats.rx_length_errors++;
561576
/* CRC error */
562-
if (err & 0x0040) {
577+
if (err & DSC_RX_ERR_CRC) {
563578
spin_lock(&priv->lock);
564579
dev->stats.rx_crc_errors++;
565580
spin_unlock(&priv->lock);
@@ -596,7 +611,7 @@ static int r6040_rx(struct net_device *dev, int limit)
596611

597612
next_descr:
598613
/* put the descriptor back to the MAC */
599-
descptr->status = 0x8000;
614+
descptr->status = DSC_OWNER_MAC;
600615
descptr = descptr->vndescp;
601616
count++;
602617
}
@@ -624,7 +639,7 @@ static void r6040_tx(struct net_device *dev)
624639
if (err & (0x2000 | 0x4000))
625640
dev->stats.tx_carrier_errors++;
626641

627-
if (descptr->status & 0x8000)
642+
if (descptr->status & DSC_OWNER_MAC)
628643
break; /* Not complete */
629644
skb_ptr = descptr->skb_ptr;
630645
pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
@@ -874,7 +889,7 @@ static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
874889
descptr->skb_ptr = skb;
875890
descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
876891
skb->data, skb->len, PCI_DMA_TODEVICE));
877-
descptr->status = 0x8000;
892+
descptr->status = DSC_OWNER_MAC;
878893
/* Trigger the MAC to check the TX descriptor */
879894
iowrite16(0x01, ioaddr + MTPR);
880895
lp->tx_insert_ptr = descptr->vndescp;

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