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horiagherbertx
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crypto: caam/qi - fix AD length endianness in S/G entry
Associated data (AD) length is read by CAAM from an S/G entry that is initially filled by the GPP. Accordingly, AD length has to be stored in CAAM endianness. Fixes: b189817 ("crypto: caam/qi - add ablkcipher and authenc algorithms") Signed-off-by: Horia Geantă <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
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drivers/crypto/caam/caamalg_qi.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -399,6 +399,7 @@ static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
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* @iv_dma: dma address of iv for checking continuity and link table
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* @qm_sg_bytes: length of dma mapped h/w link table
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* @qm_sg_dma: bus physical mapped address of h/w link table
402+
* @assoclen: associated data length, in CAAM endianness
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* @assoclen_dma: bus physical mapped address of req->assoclen
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* @drv_req: driver-specific request structure
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* @sgt: the h/w link table
@@ -409,6 +410,7 @@ struct aead_edesc {
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dma_addr_t iv_dma;
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int qm_sg_bytes;
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dma_addr_t qm_sg_dma;
413+
unsigned int assoclen;
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dma_addr_t assoclen_dma;
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struct caam_drv_req drv_req;
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#define CAAM_QI_MAX_AEAD_SG \
@@ -684,7 +686,8 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
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edesc->drv_req.cbk = aead_done;
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edesc->drv_req.drv_ctx = drv_ctx;
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687-
edesc->assoclen_dma = dma_map_single(qidev, &req->assoclen, 4,
689+
edesc->assoclen = cpu_to_caam32(req->assoclen);
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edesc->assoclen_dma = dma_map_single(qidev, &edesc->assoclen, 4,
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DMA_TO_DEVICE);
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if (dma_mapping_error(qidev, edesc->assoclen_dma)) {
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dev_err(qidev, "unable to map assoclen\n");

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