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anarsoulwens
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clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
Stop force-selecting PLL-MIPI as TCON0 parent, since it breaks video output on Pinebook that uses RGB to eDP bridge. Partially revert commit ca1170b ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux"), while still leaving CLK_SET_RATE_NO_REPARENT flag set, since we do not want the clock to be reparented. The issue is that apparently different TCON0 outputs require a different clock, or the mux might be selecting the output type. I did an experiment: I manually configured PLL_MIPI and PLL_VIDEO0_2X to the same clock rate and flipped the switch with devmem. Experiment clearly showed that whenever PLL_MIPI is selected as TCON0 clock parent, the video output stops working. Therefore, TCON0 clock parent corresponding to the output type must be assigned in the device tree. Fixes: ca1170b ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux") Reviewed-by: Dragan Simic <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Frank Oltmanns <[email protected]> # on PinePhone Tested-by: Stuart Gathman <[email protected]> # on OG Pinebook Signed-off-by: Vasily Khoruzhick <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -535,11 +535,11 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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CLK_SET_RATE_PARENT);
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/*
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* DSI output seems to work only when PLL_MIPI selected. Set it and prevent
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* the mux from reparenting.
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* Experiments showed that RGB output requires pll-video0-2x, while DSI
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* requires pll-mipi. It will not work with incorrect clock, the screen will
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* be blank.
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* sun50i-a64.dtsi assigns pll-mipi as TCON0 parent by default
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*/
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#define SUN50I_A64_TCON0_CLK_REG 0x118
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static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
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static const u8 tcon0_table[] = { 0, 2, };
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static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
@@ -959,11 +959,6 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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/* Set PLL MIPI as parent for TCON0 */
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val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
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val &= ~GENMASK(26, 24);
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writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
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ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
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if (ret)
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return ret;

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