Skip to content

Commit 384258f

Browse files
author
Roger Quadros
committed
memory: omap-gpmc: Implement IRQ domain for NAND IRQs
GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount. Use IRQ domain for this. NAND device tree node can then get the necessary interrupts by using gpmc as the interrupt parent. Legacy boot uses gpmc_get_client_irq to get the NAND interrupts from the GPMC IRQ domain. Get rid of custom bitmasks and use IRQ domain for that as well. Signed-off-by: Roger Quadros <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Tony Lindgren <[email protected]>
1 parent 512d73d commit 384258f

File tree

3 files changed

+144
-115
lines changed

3 files changed

+144
-115
lines changed

Documentation/devicetree/bindings/bus/ti-gpmc.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,12 @@ Required properties:
3232
bootloader) are used for the physical address decoding.
3333
As this will change in the future, filling correct
3434
values here is a requirement.
35+
- interrupt-controller: The GPMC driver implements and interrupt controller for
36+
the NAND events "fifoevent" and "termcount".
37+
The interrupt number mapping is as follows
38+
0 - NAND_fifoevent
39+
1 - NAND_termcount
40+
- interrupt-cells: Must be set to 2
3541

3642
Timing properties for child nodes. All are optional and default to 0.
3743

@@ -130,6 +136,8 @@ Example for an AM33xx board:
130136
#address-cells = <2>;
131137
#size-cells = <1>;
132138
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
139+
interrupt-controller;
140+
#interrupt-cells = <2>;
133141

134142
/* child nodes go here */
135143
};

0 commit comments

Comments
 (0)