@@ -594,89 +594,68 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
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IWL_DEV_INFO (0x2720 , IWL_CFG_ANY , iwl_qnj_b0_hr_b0_cfg , iwl_ax201_name ),
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/* Qu with Hr */
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- IWL_DEV_INFO (0x43F0 , 0x0044 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x43F0 , 0x0070 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x43F0 , 0x0074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x43F0 , 0x0078 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x43F0 , 0x007C , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x43F0 , 0x0244 , iwl_ax101_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x43F0 , 0x1651 , killer1650s_2ax_cfg_qu_b0_hr_b0 , NULL ),
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- IWL_DEV_INFO (0x43F0 , 0x1652 , killer1650i_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x43F0 , 0x2074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x43F0 , 0x4070 , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x43F0 , 0x4244 , iwl_ax101_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0xA0F0 , 0x0044 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x0070 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x0074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x0078 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x007C , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0xA0F0 , 0x0244 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x0A10 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x1651 , killer1650s_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x1652 , killer1650i_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x2074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0xA0F0 , 0x4070 , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0xA0F0 , 0x4244 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x0070 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x0074 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x0078 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x007C , iwl_ax201_cfg_quz_hr , NULL ),
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- IWL_DEV_INFO (0x02F0 , 0x0244 , iwl_ax101_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x0310 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x1651 , iwl_ax1650s_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x1652 , iwl_ax1650i_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x2074 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x02F0 , 0x4070 , iwl_ax201_cfg_quz_hr , NULL ),
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- IWL_DEV_INFO (0x02F0 , 0x4244 , iwl_ax101_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x0070 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x0074 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x0078 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x007C , iwl_ax201_cfg_quz_hr , NULL ),
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- IWL_DEV_INFO (0x06F0 , 0x0244 , iwl_ax101_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x0310 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x1651 , iwl_ax1650s_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x1652 , iwl_ax1650i_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x2074 , iwl_ax201_cfg_quz_hr , NULL ),
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IWL_DEV_INFO (0x06F0 , 0x4070 , iwl_ax201_cfg_quz_hr , NULL ),
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- IWL_DEV_INFO (0x06F0 , 0x4244 , iwl_ax101_cfg_quz_hr , NULL ),
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- IWL_DEV_INFO (0x34F0 , 0x0044 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x0070 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x0074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x0078 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x007C , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x34F0 , 0x0244 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x0310 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x1651 , killer1650s_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x1652 , killer1650i_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x2074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x34F0 , 0x4070 , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x34F0 , 0x4244 , iwl_ax101_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x3DF0 , 0x0044 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x0070 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x0074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x0078 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x007C , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x3DF0 , 0x0244 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x0310 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x1651 , killer1650s_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x1652 , killer1650i_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x2074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x3DF0 , 0x4070 , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x3DF0 , 0x4244 , iwl_ax101_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x4DF0 , 0x0044 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x0070 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x0074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x0078 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x007C , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x4DF0 , 0x0244 , iwl_ax101_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x0310 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x1651 , killer1650s_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x1652 , killer1650i_2ax_cfg_qu_b0_hr_b0 , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x2074 , iwl_ax201_cfg_qu_hr , NULL ),
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IWL_DEV_INFO (0x4DF0 , 0x4070 , iwl_ax201_cfg_qu_hr , NULL ),
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- IWL_DEV_INFO (0x4DF0 , 0x4244 , iwl_ax101_cfg_qu_hr , NULL ),
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_IWL_DEV_INFO (IWL_CFG_ANY , IWL_CFG_ANY ,
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IWL_CFG_MAC_TYPE_PU , IWL_CFG_ANY ,
@@ -951,6 +930,29 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
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IWL_CFG_RF_TYPE_JF2 , IWL_CFG_RF_ID_JF ,
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IWL_CFG_NO_160 , IWL_CFG_CORES_BT ,
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iwl9560_qnj_b0_jf_b0_cfg , iwl9560_killer_1550i_name ),
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+
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+ /* Qu with Hr */
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+ /* Qu B step */
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+ _IWL_DEV_INFO (IWL_CFG_ANY , IWL_CFG_ANY ,
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+ IWL_CFG_MAC_TYPE_QU , SILICON_B_STEP ,
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+ IWL_CFG_RF_TYPE_HR1 , IWL_CFG_ANY ,
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+ IWL_CFG_ANY , IWL_CFG_ANY ,
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+ iwl_qu_b0_hr1_b0 , iwl_ax101_name ),
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+
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+ /* Qu C step */
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+ _IWL_DEV_INFO (IWL_CFG_ANY , IWL_CFG_ANY ,
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+ IWL_CFG_MAC_TYPE_QU , SILICON_C_STEP ,
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+ IWL_CFG_RF_TYPE_HR1 , IWL_CFG_ANY ,
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+ IWL_CFG_ANY , IWL_CFG_ANY ,
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+ iwl_qu_c0_hr1_b0 , iwl_ax101_name ),
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+
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+ /* QuZ */
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+ _IWL_DEV_INFO (IWL_CFG_ANY , IWL_CFG_ANY ,
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+ IWL_CFG_MAC_TYPE_QUZ , IWL_CFG_ANY ,
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+ IWL_CFG_RF_TYPE_HR1 , IWL_CFG_ANY ,
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+ IWL_CFG_ANY , IWL_CFG_ANY ,
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+ iwl_quz_a0_hr1_b0 , iwl_ax101_name ),
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+
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#endif /* CONFIG_IWLMVM */
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};
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@@ -1057,9 +1059,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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* rest must be removed once we convert Qu with Hr as well.
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*/
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if (iwl_trans -> hw_rev == CSR_HW_REV_TYPE_QU_C0 ) {
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- if (iwl_trans -> cfg == & iwl_ax101_cfg_qu_hr )
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- iwl_trans -> cfg = & iwl_ax101_cfg_qu_c0_hr_b0 ;
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- else if (iwl_trans -> cfg == & iwl_ax201_cfg_qu_hr )
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+ if (iwl_trans -> cfg == & iwl_ax201_cfg_qu_hr )
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iwl_trans -> cfg = & iwl_ax201_cfg_qu_c0_hr_b0 ;
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else if (iwl_trans -> cfg == & killer1650s_2ax_cfg_qu_b0_hr_b0 )
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iwl_trans -> cfg = & killer1650s_2ax_cfg_qu_c0_hr_b0 ;
@@ -1069,9 +1069,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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/* same thing for QuZ... */
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if (iwl_trans -> hw_rev == CSR_HW_REV_TYPE_QUZ ) {
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- if (iwl_trans -> cfg == & iwl_ax101_cfg_qu_hr )
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- iwl_trans -> cfg = & iwl_ax101_cfg_quz_hr ;
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- else if (iwl_trans -> cfg == & iwl_ax201_cfg_qu_hr )
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+ if (iwl_trans -> cfg == & iwl_ax201_cfg_qu_hr )
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iwl_trans -> cfg = & iwl_ax201_cfg_quz_hr ;
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}
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