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net/mlx5_fpga: Drop INNOVA TLS support
Mellanox INNOVA TLS cards are EOL in May, 2018 [1]. As such, the code is unmaintained, untested and not in-use by any upstream/distro oriented customers. In order to reduce code complexity, drop the kernel code. [1] https://network.nvidia.com/related-docs/eol/LCR-000286.pdf Link: https://lore.kernel.org/r/b88add368def721ea9d054cb69def72d9e3f67aa.1649073691.git.leonro@nvidia.com Reviewed-by: Tariq Toukan <[email protected]> Reviewed-by: Saeed Mahameed <[email protected]> Signed-off-by: Leon Romanovsky <[email protected]>
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drivers/net/ethernet/mellanox/mlx5/core/Kconfig

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -177,20 +177,6 @@ config MLX5_EN_IPSEC
177177
Note: Support for hardware with this capability needs to be selected
178178
for this option to become available.
179179

180-
config MLX5_FPGA_TLS
181-
bool "Mellanox Technologies TLS Innova support"
182-
depends on TLS_DEVICE
183-
depends on TLS=y || MLX5_CORE=m
184-
depends on MLX5_CORE_EN
185-
depends on MLX5_FPGA
186-
select MLX5_EN_TLS
187-
help
188-
Build TLS support for the Innova family of network cards by Mellanox
189-
Technologies. Innova network cards are comprised of a ConnectX chip
190-
and an FPGA chip on one board. If you select this option, the
191-
mlx5_core driver will include the Innova FPGA core and allow building
192-
sandbox-specific client drivers.
193-
194180
config MLX5_TLS
195181
bool "Mellanox Technologies TLS Connect-X support"
196182
depends on TLS_DEVICE

drivers/net/ethernet/mellanox/mlx5/core/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,6 @@ mlx5_core-$(CONFIG_MLX5_CORE_IPOIB) += ipoib/ipoib.o ipoib/ethtool.o ipoib/ipoib
9090
#
9191
mlx5_core-$(CONFIG_MLX5_IPSEC) += accel/ipsec_offload.o
9292
mlx5_core-$(CONFIG_MLX5_FPGA_IPSEC) += fpga/ipsec.o
93-
mlx5_core-$(CONFIG_MLX5_FPGA_TLS) += fpga/tls.o
9493
mlx5_core-$(CONFIG_MLX5_ACCEL) += lib/crypto.o accel/tls.o accel/ipsec.o
9594

9695
mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o

drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c

Lines changed: 0 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -37,53 +37,6 @@
3737
#include "mlx5_core.h"
3838
#include "lib/mlx5.h"
3939

40-
#ifdef CONFIG_MLX5_FPGA_TLS
41-
#include "fpga/tls.h"
42-
43-
int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
44-
struct tls_crypto_info *crypto_info,
45-
u32 start_offload_tcp_sn, u32 *p_swid,
46-
bool direction_sx)
47-
{
48-
return mlx5_fpga_tls_add_flow(mdev, flow, crypto_info,
49-
start_offload_tcp_sn, p_swid,
50-
direction_sx);
51-
}
52-
53-
void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
54-
bool direction_sx)
55-
{
56-
mlx5_fpga_tls_del_flow(mdev, swid, GFP_KERNEL, direction_sx);
57-
}
58-
59-
int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
60-
u32 seq, __be64 rcd_sn)
61-
{
62-
return mlx5_fpga_tls_resync_rx(mdev, handle, seq, rcd_sn);
63-
}
64-
65-
bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
66-
{
67-
return mlx5_fpga_is_tls_device(mdev) ||
68-
mlx5_accel_is_ktls_device(mdev);
69-
}
70-
71-
u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev)
72-
{
73-
return mlx5_fpga_tls_device_caps(mdev);
74-
}
75-
76-
int mlx5_accel_tls_init(struct mlx5_core_dev *mdev)
77-
{
78-
return mlx5_fpga_tls_init(mdev);
79-
}
80-
81-
void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev)
82-
{
83-
mlx5_fpga_tls_cleanup(mdev);
84-
}
85-
#endif
86-
8740
#ifdef CONFIG_MLX5_TLS
8841
int mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
8942
struct tls_crypto_info *crypto_info,

drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h

Lines changed: 0 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -97,60 +97,4 @@ static inline bool
9797
mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
9898
struct tls_crypto_info *crypto_info) { return false; }
9999
#endif
100-
101-
enum {
102-
MLX5_ACCEL_TLS_TX = BIT(0),
103-
MLX5_ACCEL_TLS_RX = BIT(1),
104-
MLX5_ACCEL_TLS_V12 = BIT(2),
105-
MLX5_ACCEL_TLS_V13 = BIT(3),
106-
MLX5_ACCEL_TLS_LRO = BIT(4),
107-
MLX5_ACCEL_TLS_IPV6 = BIT(5),
108-
MLX5_ACCEL_TLS_AES_GCM128 = BIT(30),
109-
MLX5_ACCEL_TLS_AES_GCM256 = BIT(31),
110-
};
111-
112-
struct mlx5_ifc_tls_flow_bits {
113-
u8 src_port[0x10];
114-
u8 dst_port[0x10];
115-
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
116-
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
117-
u8 ipv6[0x1];
118-
u8 direction_sx[0x1];
119-
u8 reserved_at_2[0x1e];
120-
};
121-
122-
#ifdef CONFIG_MLX5_FPGA_TLS
123-
int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
124-
struct tls_crypto_info *crypto_info,
125-
u32 start_offload_tcp_sn, u32 *p_swid,
126-
bool direction_sx);
127-
void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
128-
bool direction_sx);
129-
int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
130-
u32 seq, __be64 rcd_sn);
131-
bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev);
132-
u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev);
133-
int mlx5_accel_tls_init(struct mlx5_core_dev *mdev);
134-
void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev);
135-
136-
#else
137-
138-
static inline int
139-
mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
140-
struct tls_crypto_info *crypto_info,
141-
u32 start_offload_tcp_sn, u32 *p_swid,
142-
bool direction_sx) { return -ENOTSUPP; }
143-
static inline void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
144-
bool direction_sx) { }
145-
static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
146-
u32 seq, __be64 rcd_sn) { return 0; }
147-
static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
148-
{
149-
return mlx5_accel_is_ktls_device(mdev);
150-
}
151-
static inline u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev) { return 0; }
152-
static inline int mlx5_accel_tls_init(struct mlx5_core_dev *mdev) { return 0; }
153-
static inline void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev) { }
154-
#endif
155-
156100
#endif /* __MLX5_ACCEL_TLS_H__ */

drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -354,7 +354,6 @@ enum {
354354
MLX5E_RQ_STATE_AM,
355355
MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
356356
MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
357-
MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
358357
MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
359358
MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
360359
};

drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls.c

Lines changed: 2 additions & 178 deletions
Original file line numberDiff line numberDiff line change
@@ -36,188 +36,12 @@
3636
#include "en_accel/tls.h"
3737
#include "accel/tls.h"
3838

39-
static void mlx5e_tls_set_ipv4_flow(void *flow, struct sock *sk)
40-
{
41-
struct inet_sock *inet = inet_sk(sk);
42-
43-
MLX5_SET(tls_flow, flow, ipv6, 0);
44-
memcpy(MLX5_ADDR_OF(tls_flow, flow, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
45-
&inet->inet_daddr, MLX5_FLD_SZ_BYTES(ipv4_layout, ipv4));
46-
memcpy(MLX5_ADDR_OF(tls_flow, flow, src_ipv4_src_ipv6.ipv4_layout.ipv4),
47-
&inet->inet_rcv_saddr, MLX5_FLD_SZ_BYTES(ipv4_layout, ipv4));
48-
}
49-
50-
#if IS_ENABLED(CONFIG_IPV6)
51-
static void mlx5e_tls_set_ipv6_flow(void *flow, struct sock *sk)
52-
{
53-
struct ipv6_pinfo *np = inet6_sk(sk);
54-
55-
MLX5_SET(tls_flow, flow, ipv6, 1);
56-
memcpy(MLX5_ADDR_OF(tls_flow, flow, dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
57-
&sk->sk_v6_daddr, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
58-
memcpy(MLX5_ADDR_OF(tls_flow, flow, src_ipv4_src_ipv6.ipv6_layout.ipv6),
59-
&np->saddr, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
60-
}
61-
#endif
62-
63-
static void mlx5e_tls_set_flow_tcp_ports(void *flow, struct sock *sk)
64-
{
65-
struct inet_sock *inet = inet_sk(sk);
66-
67-
memcpy(MLX5_ADDR_OF(tls_flow, flow, src_port), &inet->inet_sport,
68-
MLX5_FLD_SZ_BYTES(tls_flow, src_port));
69-
memcpy(MLX5_ADDR_OF(tls_flow, flow, dst_port), &inet->inet_dport,
70-
MLX5_FLD_SZ_BYTES(tls_flow, dst_port));
71-
}
72-
73-
static int mlx5e_tls_set_flow(void *flow, struct sock *sk, u32 caps)
74-
{
75-
switch (sk->sk_family) {
76-
case AF_INET:
77-
mlx5e_tls_set_ipv4_flow(flow, sk);
78-
break;
79-
#if IS_ENABLED(CONFIG_IPV6)
80-
case AF_INET6:
81-
if (!sk->sk_ipv6only &&
82-
ipv6_addr_type(&sk->sk_v6_daddr) == IPV6_ADDR_MAPPED) {
83-
mlx5e_tls_set_ipv4_flow(flow, sk);
84-
break;
85-
}
86-
if (!(caps & MLX5_ACCEL_TLS_IPV6))
87-
goto error_out;
88-
89-
mlx5e_tls_set_ipv6_flow(flow, sk);
90-
break;
91-
#endif
92-
default:
93-
goto error_out;
94-
}
95-
96-
mlx5e_tls_set_flow_tcp_ports(flow, sk);
97-
return 0;
98-
error_out:
99-
return -EINVAL;
100-
}
101-
102-
static int mlx5e_tls_add(struct net_device *netdev, struct sock *sk,
103-
enum tls_offload_ctx_dir direction,
104-
struct tls_crypto_info *crypto_info,
105-
u32 start_offload_tcp_sn)
106-
{
107-
struct mlx5e_priv *priv = netdev_priv(netdev);
108-
struct tls_context *tls_ctx = tls_get_ctx(sk);
109-
struct mlx5_core_dev *mdev = priv->mdev;
110-
u32 caps = mlx5_accel_tls_device_caps(mdev);
111-
int ret = -ENOMEM;
112-
void *flow;
113-
u32 swid;
114-
115-
flow = kzalloc(MLX5_ST_SZ_BYTES(tls_flow), GFP_KERNEL);
116-
if (!flow)
117-
return ret;
118-
119-
ret = mlx5e_tls_set_flow(flow, sk, caps);
120-
if (ret)
121-
goto free_flow;
122-
123-
ret = mlx5_accel_tls_add_flow(mdev, flow, crypto_info,
124-
start_offload_tcp_sn, &swid,
125-
direction == TLS_OFFLOAD_CTX_DIR_TX);
126-
if (ret < 0)
127-
goto free_flow;
128-
129-
if (direction == TLS_OFFLOAD_CTX_DIR_TX) {
130-
struct mlx5e_tls_offload_context_tx *tx_ctx =
131-
mlx5e_get_tls_tx_context(tls_ctx);
132-
133-
tx_ctx->swid = htonl(swid);
134-
tx_ctx->expected_seq = start_offload_tcp_sn;
135-
} else {
136-
struct mlx5e_tls_offload_context_rx *rx_ctx =
137-
mlx5e_get_tls_rx_context(tls_ctx);
138-
139-
rx_ctx->handle = htonl(swid);
140-
}
141-
142-
return 0;
143-
free_flow:
144-
kfree(flow);
145-
return ret;
146-
}
147-
148-
static void mlx5e_tls_del(struct net_device *netdev,
149-
struct tls_context *tls_ctx,
150-
enum tls_offload_ctx_dir direction)
151-
{
152-
struct mlx5e_priv *priv = netdev_priv(netdev);
153-
unsigned int handle;
154-
155-
handle = ntohl((direction == TLS_OFFLOAD_CTX_DIR_TX) ?
156-
mlx5e_get_tls_tx_context(tls_ctx)->swid :
157-
mlx5e_get_tls_rx_context(tls_ctx)->handle);
158-
159-
mlx5_accel_tls_del_flow(priv->mdev, handle,
160-
direction == TLS_OFFLOAD_CTX_DIR_TX);
161-
}
162-
163-
static int mlx5e_tls_resync(struct net_device *netdev, struct sock *sk,
164-
u32 seq, u8 *rcd_sn_data,
165-
enum tls_offload_ctx_dir direction)
166-
{
167-
struct tls_context *tls_ctx = tls_get_ctx(sk);
168-
struct mlx5e_priv *priv = netdev_priv(netdev);
169-
struct mlx5e_tls_offload_context_rx *rx_ctx;
170-
__be64 rcd_sn = *(__be64 *)rcd_sn_data;
171-
172-
if (WARN_ON_ONCE(direction != TLS_OFFLOAD_CTX_DIR_RX))
173-
return -EINVAL;
174-
rx_ctx = mlx5e_get_tls_rx_context(tls_ctx);
175-
176-
netdev_info(netdev, "resyncing seq %d rcd %lld\n", seq,
177-
be64_to_cpu(rcd_sn));
178-
mlx5_accel_tls_resync_rx(priv->mdev, rx_ctx->handle, seq, rcd_sn);
179-
atomic64_inc(&priv->tls->sw_stats.rx_tls_resync_reply);
180-
181-
return 0;
182-
}
183-
184-
static const struct tlsdev_ops mlx5e_tls_ops = {
185-
.tls_dev_add = mlx5e_tls_add,
186-
.tls_dev_del = mlx5e_tls_del,
187-
.tls_dev_resync = mlx5e_tls_resync,
188-
};
189-
19039
void mlx5e_tls_build_netdev(struct mlx5e_priv *priv)
19140
{
192-
struct net_device *netdev = priv->netdev;
193-
u32 caps;
194-
195-
if (mlx5e_accel_is_ktls_device(priv->mdev)) {
196-
mlx5e_ktls_build_netdev(priv);
41+
if (!mlx5e_accel_is_ktls_device(priv->mdev))
19742
return;
198-
}
199-
200-
/* FPGA */
201-
if (!mlx5e_accel_is_tls_device(priv->mdev))
202-
return;
203-
204-
caps = mlx5_accel_tls_device_caps(priv->mdev);
205-
if (caps & MLX5_ACCEL_TLS_TX) {
206-
netdev->features |= NETIF_F_HW_TLS_TX;
207-
netdev->hw_features |= NETIF_F_HW_TLS_TX;
208-
}
209-
210-
if (caps & MLX5_ACCEL_TLS_RX) {
211-
netdev->features |= NETIF_F_HW_TLS_RX;
212-
netdev->hw_features |= NETIF_F_HW_TLS_RX;
213-
}
214-
215-
if (!(caps & MLX5_ACCEL_TLS_LRO)) {
216-
netdev->features &= ~NETIF_F_LRO;
217-
netdev->hw_features &= ~NETIF_F_LRO;
218-
}
21943

220-
netdev->tlsdev_ops = &mlx5e_tls_ops;
44+
mlx5e_ktls_build_netdev(priv);
22145
}
22246

22347
int mlx5e_tls_init(struct mlx5e_priv *priv)

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