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mripardmripard
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drm: Rename plane->state variables in atomic update and disable
Some drivers are storing the plane->state pointer in atomic_update and atomic_disable in a variable simply called state, while the state passed as an argument is called old_state. In order to ease subsequent reworks and to avoid confusing or inconsistent names, let's rename those variables to new_state. This was done using the following coccinelle script, plus some manual changes for mtk and tegra. @ plane_atomic_func @ identifier helpers; identifier func; @@ ( static const struct drm_plane_helper_funcs helpers = { ..., .atomic_disable = func, ..., }; | static const struct drm_plane_helper_funcs helpers = { ..., .atomic_update = func, ..., }; ) @ moves_new_state_old_state @ identifier plane_atomic_func.func; identifier plane; symbol old_state; symbol state; @@ func(struct drm_plane *plane, struct drm_plane_state *old_state) { ... - struct drm_plane_state *state = plane->state; + struct drm_plane_state *new_state = plane->state; ... } @ depends on moves_new_state_old_state @ identifier plane_atomic_func.func; identifier plane; identifier old_state; symbol state; @@ func(struct drm_plane *plane, struct drm_plane_state *old_state) { <... - state + new_state ...> } @ moves_new_state_oldstate @ identifier plane_atomic_func.func; identifier plane; symbol oldstate; symbol state; @@ func(struct drm_plane *plane, struct drm_plane_state *oldstate) { ... - struct drm_plane_state *state = plane->state; + struct drm_plane_state *newstate = plane->state; ... } @ depends on moves_new_state_oldstate @ identifier plane_atomic_func.func; identifier plane; identifier old_state; symbol state; @@ func(struct drm_plane *plane, struct drm_plane_state *old_state) { <... - state + newstate ...> } @ moves_new_state_old_pstate @ identifier plane_atomic_func.func; identifier plane; symbol old_pstate; symbol state; @@ func(struct drm_plane *plane, struct drm_plane_state *old_pstate) { ... - struct drm_plane_state *state = plane->state; + struct drm_plane_state *new_pstate = plane->state; ... } @ depends on moves_new_state_old_pstate @ identifier plane_atomic_func.func; identifier plane; identifier old_pstate; symbol state; @@ func(struct drm_plane *plane, struct drm_plane_state *old_pstate) { <... - state + new_pstate ...> } Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
1 parent e05162c commit 41016fe

30 files changed

+355
-347
lines changed

‎drivers/gpu/drm/arm/malidp_planes.c

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -795,9 +795,9 @@ static void malidp_de_plane_update(struct drm_plane *plane,
795795
{
796796
struct malidp_plane *mp;
797797
struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
798-
struct drm_plane_state *state = plane->state;
799-
u16 pixel_alpha = state->pixel_blend_mode;
800-
u8 plane_alpha = state->alpha >> 8;
798+
struct drm_plane_state *new_state = plane->state;
799+
u16 pixel_alpha = new_state->pixel_blend_mode;
800+
u8 plane_alpha = new_state->alpha >> 8;
801801
u32 src_w, src_h, dest_w, dest_h, val;
802802
int i;
803803
struct drm_framebuffer *fb = plane->state->fb;
@@ -813,12 +813,12 @@ static void malidp_de_plane_update(struct drm_plane *plane,
813813
src_h = fb->height;
814814
} else {
815815
/* convert src values from Q16 fixed point to integer */
816-
src_w = state->src_w >> 16;
817-
src_h = state->src_h >> 16;
816+
src_w = new_state->src_w >> 16;
817+
src_h = new_state->src_h >> 16;
818818
}
819819

820-
dest_w = state->crtc_w;
821-
dest_h = state->crtc_h;
820+
dest_w = new_state->crtc_w;
821+
dest_h = new_state->crtc_h;
822822

823823
val = malidp_hw_read(mp->hwdev, mp->layer->base);
824824
val = (val & ~LAYER_FORMAT_MASK) | ms->format;
@@ -830,7 +830,7 @@ static void malidp_de_plane_update(struct drm_plane *plane,
830830
malidp_de_set_mmu_control(mp, ms);
831831

832832
malidp_de_set_plane_pitches(mp, ms->n_planes,
833-
state->fb->pitches);
833+
new_state->fb->pitches);
834834

835835
if ((plane->state->color_encoding != old_state->color_encoding) ||
836836
(plane->state->color_range != old_state->color_range))
@@ -843,8 +843,8 @@ static void malidp_de_plane_update(struct drm_plane *plane,
843843
malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
844844
mp->layer->base + MALIDP_LAYER_COMP_SIZE);
845845

846-
malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) |
847-
LAYER_V_VAL(state->crtc_y),
846+
malidp_hw_write(mp->hwdev, LAYER_H_VAL(new_state->crtc_x) |
847+
LAYER_V_VAL(new_state->crtc_y),
848848
mp->layer->base + MALIDP_LAYER_OFFSET);
849849

850850
if (mp->layer->id == DE_SMART) {
@@ -866,19 +866,19 @@ static void malidp_de_plane_update(struct drm_plane *plane,
866866
val &= ~LAYER_ROT_MASK;
867867

868868
/* setup the rotation and axis flip bits */
869-
if (state->rotation & DRM_MODE_ROTATE_MASK)
869+
if (new_state->rotation & DRM_MODE_ROTATE_MASK)
870870
val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
871871
LAYER_ROT_OFFSET;
872-
if (state->rotation & DRM_MODE_REFLECT_X)
872+
if (new_state->rotation & DRM_MODE_REFLECT_X)
873873
val |= LAYER_H_FLIP;
874-
if (state->rotation & DRM_MODE_REFLECT_Y)
874+
if (new_state->rotation & DRM_MODE_REFLECT_Y)
875875
val |= LAYER_V_FLIP;
876876

877877
val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff));
878878

879-
if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) {
879+
if (new_state->alpha != DRM_BLEND_ALPHA_OPAQUE) {
880880
val |= LAYER_COMP_PLANE;
881-
} else if (state->fb->format->has_alpha) {
881+
} else if (new_state->fb->format->has_alpha) {
882882
/* We only care about blend mode if the format has alpha */
883883
switch (pixel_alpha) {
884884
case DRM_MODE_BLEND_PREMULTI:
@@ -892,9 +892,9 @@ static void malidp_de_plane_update(struct drm_plane *plane,
892892
val |= LAYER_ALPHA(plane_alpha);
893893

894894
val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
895-
if (state->crtc) {
895+
if (new_state->crtc) {
896896
struct malidp_crtc_state *m =
897-
to_malidp_crtc_state(state->crtc->state);
897+
to_malidp_crtc_state(new_state->crtc->state);
898898

899899
if (m->scaler_config.scale_enable &&
900900
m->scaler_config.plane_src_id == mp->layer->id)

‎drivers/gpu/drm/armada/armada_overlay.c

Lines changed: 53 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -68,141 +68,143 @@ static inline u32 armada_csc(struct drm_plane_state *state)
6868
static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
6969
struct drm_plane_state *old_state)
7070
{
71-
struct drm_plane_state *state = plane->state;
71+
struct drm_plane_state *new_state = plane->state;
7272
struct armada_crtc *dcrtc;
7373
struct armada_regs *regs;
7474
unsigned int idx;
7575
u32 cfg, cfg_mask, val;
7676

7777
DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
7878

79-
if (!state->fb || WARN_ON(!state->crtc))
79+
if (!new_state->fb || WARN_ON(!new_state->crtc))
8080
return;
8181

8282
DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
8383
plane->base.id, plane->name,
84-
state->crtc->base.id, state->crtc->name,
85-
state->fb->base.id,
86-
old_state->visible, state->visible);
84+
new_state->crtc->base.id, new_state->crtc->name,
85+
new_state->fb->base.id,
86+
old_state->visible, new_state->visible);
8787

88-
dcrtc = drm_to_armada_crtc(state->crtc);
88+
dcrtc = drm_to_armada_crtc(new_state->crtc);
8989
regs = dcrtc->regs + dcrtc->regs_idx;
9090

9191
idx = 0;
92-
if (!old_state->visible && state->visible)
92+
if (!old_state->visible && new_state->visible)
9393
armada_reg_queue_mod(regs, idx,
9494
0, CFG_PDWN16x66 | CFG_PDWN32x66,
9595
LCD_SPU_SRAM_PARA1);
96-
val = armada_src_hw(state);
96+
val = armada_src_hw(new_state);
9797
if (armada_src_hw(old_state) != val)
9898
armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
99-
val = armada_dst_yx(state);
99+
val = armada_dst_yx(new_state);
100100
if (armada_dst_yx(old_state) != val)
101101
armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
102-
val = armada_dst_hw(state);
102+
val = armada_dst_hw(new_state);
103103
if (armada_dst_hw(old_state) != val)
104104
armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
105105
/* FIXME: overlay on an interlaced display */
106-
if (old_state->src.x1 != state->src.x1 ||
107-
old_state->src.y1 != state->src.y1 ||
108-
old_state->fb != state->fb ||
109-
state->crtc->state->mode_changed) {
106+
if (old_state->src.x1 != new_state->src.x1 ||
107+
old_state->src.y1 != new_state->src.y1 ||
108+
old_state->fb != new_state->fb ||
109+
new_state->crtc->state->mode_changed) {
110110
const struct drm_format_info *format;
111111
u16 src_x;
112112

113-
armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
113+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
114114
LCD_SPU_DMA_START_ADDR_Y0);
115-
armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1),
115+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),
116116
LCD_SPU_DMA_START_ADDR_U0);
117-
armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2),
117+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),
118118
LCD_SPU_DMA_START_ADDR_V0);
119-
armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
119+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
120120
LCD_SPU_DMA_START_ADDR_Y1);
121-
armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1),
121+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),
122122
LCD_SPU_DMA_START_ADDR_U1);
123-
armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2),
123+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),
124124
LCD_SPU_DMA_START_ADDR_V1);
125125

126-
val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0);
126+
val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state,
127+
0);
127128
armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
128-
val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2);
129+
val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state,
130+
2);
129131
armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
130132

131-
cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
132-
CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) |
133+
cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
134+
CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) |
133135
CFG_CBSH_ENA;
134-
if (state->visible)
136+
if (new_state->visible)
135137
cfg |= CFG_DMA_ENA;
136138

137139
/*
138140
* Shifting a YUV packed format image by one pixel causes the
139141
* U/V planes to swap. Compensate for it by also toggling
140142
* the UV swap.
141143
*/
142-
format = state->fb->format;
143-
src_x = state->src.x1 >> 16;
144+
format = new_state->fb->format;
145+
src_x = new_state->src.x1 >> 16;
144146
if (format->num_planes == 1 && src_x & (format->hsub - 1))
145147
cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
146-
if (to_armada_plane_state(state)->interlace)
148+
if (to_armada_plane_state(new_state)->interlace)
147149
cfg |= CFG_DMA_FTOGGLE;
148150
cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
149151
CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
150152
CFG_SWAPYU | CFG_YUV2RGB) |
151153
CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
152154
CFG_DMA_ENA;
153-
} else if (old_state->visible != state->visible) {
154-
cfg = state->visible ? CFG_DMA_ENA : 0;
155+
} else if (old_state->visible != new_state->visible) {
156+
cfg = new_state->visible ? CFG_DMA_ENA : 0;
155157
cfg_mask = CFG_DMA_ENA;
156158
} else {
157159
cfg = cfg_mask = 0;
158160
}
159-
if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
160-
drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
161+
if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
162+
drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
161163
cfg_mask |= CFG_DMA_HSMOOTH;
162-
if (drm_rect_width(&state->src) >> 16 !=
163-
drm_rect_width(&state->dst))
164+
if (drm_rect_width(&new_state->src) >> 16 !=
165+
drm_rect_width(&new_state->dst))
164166
cfg |= CFG_DMA_HSMOOTH;
165167
}
166168

167169
if (cfg_mask)
168170
armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
169171
LCD_SPU_DMA_CTRL0);
170172

171-
val = armada_spu_contrast(state);
172-
if ((!old_state->visible && state->visible) ||
173+
val = armada_spu_contrast(new_state);
174+
if ((!old_state->visible && new_state->visible) ||
173175
armada_spu_contrast(old_state) != val)
174176
armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
175-
val = armada_spu_saturation(state);
176-
if ((!old_state->visible && state->visible) ||
177+
val = armada_spu_saturation(new_state);
178+
if ((!old_state->visible && new_state->visible) ||
177179
armada_spu_saturation(old_state) != val)
178180
armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
179-
if (!old_state->visible && state->visible)
181+
if (!old_state->visible && new_state->visible)
180182
armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
181-
val = armada_csc(state);
182-
if ((!old_state->visible && state->visible) ||
183+
val = armada_csc(new_state);
184+
if ((!old_state->visible && new_state->visible) ||
183185
armada_csc(old_state) != val)
184186
armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,
185187
LCD_SPU_IOPAD_CONTROL);
186-
val = drm_to_overlay_state(state)->colorkey_yr;
187-
if ((!old_state->visible && state->visible) ||
188+
val = drm_to_overlay_state(new_state)->colorkey_yr;
189+
if ((!old_state->visible && new_state->visible) ||
188190
drm_to_overlay_state(old_state)->colorkey_yr != val)
189191
armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
190-
val = drm_to_overlay_state(state)->colorkey_ug;
191-
if ((!old_state->visible && state->visible) ||
192+
val = drm_to_overlay_state(new_state)->colorkey_ug;
193+
if ((!old_state->visible && new_state->visible) ||
192194
drm_to_overlay_state(old_state)->colorkey_ug != val)
193195
armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
194-
val = drm_to_overlay_state(state)->colorkey_vb;
195-
if ((!old_state->visible && state->visible) ||
196+
val = drm_to_overlay_state(new_state)->colorkey_vb;
197+
if ((!old_state->visible && new_state->visible) ||
196198
drm_to_overlay_state(old_state)->colorkey_vb != val)
197199
armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
198-
val = drm_to_overlay_state(state)->colorkey_mode;
199-
if ((!old_state->visible && state->visible) ||
200+
val = drm_to_overlay_state(new_state)->colorkey_mode;
201+
if ((!old_state->visible && new_state->visible) ||
200202
drm_to_overlay_state(old_state)->colorkey_mode != val)
201203
armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |
202204
CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
203205
LCD_SPU_DMA_CTRL1);
204-
val = drm_to_overlay_state(state)->colorkey_enable;
205-
if (((!old_state->visible && state->visible) ||
206+
val = drm_to_overlay_state(new_state)->colorkey_enable;
207+
if (((!old_state->visible && new_state->visible) ||
206208
drm_to_overlay_state(old_state)->colorkey_enable != val) &&
207209
dcrtc->variant->has_spu_adv_reg)
208210
armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |

‎drivers/gpu/drm/armada/armada_plane.c

Lines changed: 32 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -163,79 +163,80 @@ int armada_drm_plane_atomic_check(struct drm_plane *plane,
163163
static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
164164
struct drm_plane_state *old_state)
165165
{
166-
struct drm_plane_state *state = plane->state;
166+
struct drm_plane_state *new_state = plane->state;
167167
struct armada_crtc *dcrtc;
168168
struct armada_regs *regs;
169169
u32 cfg, cfg_mask, val;
170170
unsigned int idx;
171171

172172
DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
173173

174-
if (!state->fb || WARN_ON(!state->crtc))
174+
if (!new_state->fb || WARN_ON(!new_state->crtc))
175175
return;
176176

177177
DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
178178
plane->base.id, plane->name,
179-
state->crtc->base.id, state->crtc->name,
180-
state->fb->base.id,
181-
old_state->visible, state->visible);
179+
new_state->crtc->base.id, new_state->crtc->name,
180+
new_state->fb->base.id,
181+
old_state->visible, new_state->visible);
182182

183-
dcrtc = drm_to_armada_crtc(state->crtc);
183+
dcrtc = drm_to_armada_crtc(new_state->crtc);
184184
regs = dcrtc->regs + dcrtc->regs_idx;
185185

186186
idx = 0;
187-
if (!old_state->visible && state->visible) {
187+
if (!old_state->visible && new_state->visible) {
188188
val = CFG_PDWN64x66;
189-
if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
189+
if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)
190190
val |= CFG_PDWN256x24;
191191
armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
192192
}
193-
val = armada_src_hw(state);
193+
val = armada_src_hw(new_state);
194194
if (armada_src_hw(old_state) != val)
195195
armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
196-
val = armada_dst_yx(state);
196+
val = armada_dst_yx(new_state);
197197
if (armada_dst_yx(old_state) != val)
198198
armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
199-
val = armada_dst_hw(state);
199+
val = armada_dst_hw(new_state);
200200
if (armada_dst_hw(old_state) != val)
201201
armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
202-
if (old_state->src.x1 != state->src.x1 ||
203-
old_state->src.y1 != state->src.y1 ||
204-
old_state->fb != state->fb ||
205-
state->crtc->state->mode_changed) {
206-
armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
202+
if (old_state->src.x1 != new_state->src.x1 ||
203+
old_state->src.y1 != new_state->src.y1 ||
204+
old_state->fb != new_state->fb ||
205+
new_state->crtc->state->mode_changed) {
206+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
207207
LCD_CFG_GRA_START_ADDR0);
208-
armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
208+
armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
209209
LCD_CFG_GRA_START_ADDR1);
210-
armada_reg_queue_mod(regs, idx, armada_pitch(state, 0), 0xffff,
210+
armada_reg_queue_mod(regs, idx, armada_pitch(new_state, 0),
211+
0xffff,
211212
LCD_CFG_GRA_PITCH);
212213
}
213-
if (old_state->fb != state->fb ||
214-
state->crtc->state->mode_changed) {
215-
cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
216-
CFG_GRA_MOD(drm_fb_to_armada_fb(state->fb)->mod);
217-
if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
214+
if (old_state->fb != new_state->fb ||
215+
new_state->crtc->state->mode_changed) {
216+
cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
217+
CFG_GRA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod);
218+
if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)
218219
cfg |= CFG_PALETTE_ENA;
219-
if (state->visible)
220+
if (new_state->visible)
220221
cfg |= CFG_GRA_ENA;
221-
if (to_armada_plane_state(state)->interlace)
222+
if (to_armada_plane_state(new_state)->interlace)
222223
cfg |= CFG_GRA_FTOGGLE;
223224
cfg_mask = CFG_GRAFORMAT |
224225
CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
225226
CFG_SWAPYU | CFG_YUV2RGB) |
226227
CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
227228
CFG_GRA_ENA;
228-
} else if (old_state->visible != state->visible) {
229-
cfg = state->visible ? CFG_GRA_ENA : 0;
229+
} else if (old_state->visible != new_state->visible) {
230+
cfg = new_state->visible ? CFG_GRA_ENA : 0;
230231
cfg_mask = CFG_GRA_ENA;
231232
} else {
232233
cfg = cfg_mask = 0;
233234
}
234-
if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
235-
drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
235+
if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
236+
drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
236237
cfg_mask |= CFG_GRA_HSMOOTH;
237-
if (drm_rect_width(&state->src) >> 16 !=
238-
drm_rect_width(&state->dst))
238+
if (drm_rect_width(&new_state->src) >> 16 !=
239+
drm_rect_width(&new_state->dst))
239240
cfg |= CFG_GRA_HSMOOTH;
240241
}
241242

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