x86/microcode: add SPEC_CTRL_SSBD to x86_spec_ctrl_mask on late loading.

This is required so that we don't filter out the SPEC_CTRL_SSBD bit from
what the guest is trying to write to the MSR_IA32_SPEC_CTRL in
x86_virt_spec_ctrl().  Failure to do would make it look like the guest
correctly enabled SSBD when it did not, as reading back the MSR from the
guest would not show the bit was filtered out, giving a false sense of
security.

Orabug: 29642139

Reported-by: Quentin Casasnovas <[email protected]>
Signed-off-by: Mihai Carabas <[email protected]>
Reviewed-by: Boris Ostrovsky <[email protected]>
Signed-off-by: Brian Maly <[email protected]>

Author: mcarabas

arch/x86/kernel/cpu/bugs_64.c

@@ -1551,6 +1551,7 @@ void microcode_late_select_mitigation(void)
 			else
 				ssb_mode = SPEC_STORE_BYPASS_PRCTL;
 		}
+		x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 #undef pr_fmt
 #define pr_fmt(fmt)	"Speculative Store Bypass late loading: " fmt
 		pr_info("%s\n", ssb_strings[ssb_mode]);