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Alex Elderdavem330
Alex Elder
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davem330
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net: ipa: add "gsi_v3.5.1.c"
The next patch adds a GSI register field that is only valid starting at IPA v3.5.1. Create "gsi_v3.5.1.c" from "gsi_v3.1.c", changing only the name of the public regs structure it defines. Signed-off-by: Alex Elder <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ipa/Makefile

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@@ -5,7 +5,7 @@
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IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11
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# Some IPA versions can reuse another set of GSI register definitions.
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GSI_IPA_VERSIONS := 3.1
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GSI_IPA_VERSIONS := 3.1 3.5.1
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obj-$(CONFIG_QCOM_IPA) += ipa.o
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‎drivers/net/ipa/gsi_reg.h

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@@ -320,6 +320,7 @@ enum gsi_generic_ee_result {
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};
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extern const struct regs gsi_regs_v3_1;
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extern const struct regs gsi_regs_v3_5_1;
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/**
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* gsi_reg() - Return the structure describing a GSI register

‎drivers/net/ipa/reg/gsi_reg-v3.5.1.c

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@@ -0,0 +1,183 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2023 Linaro Ltd. */
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#include <linux/types.h>
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#include "../gsi.h"
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#include "../reg.h"
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#include "../gsi_reg.h"
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/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
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REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
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0x0000c020 + 0x1000 * GSI_EE_AP);
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REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
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0x0000c024 + 0x1000 * GSI_EE_AP);
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/* All other register offsets are relative to gsi->virt */
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REG_STRIDE(CH_C_CNTXT_0, ch_c_cntxt_0, 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_CNTXT_1, ch_c_cntxt_1, 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
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0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
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0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
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0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
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0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
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0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
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0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
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0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
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0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
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0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
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0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
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0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
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0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
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0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
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0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
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0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
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0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
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0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
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0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
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REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
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0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
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REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
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0x0001f098 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
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0x0001f09c + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
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0x0001f0a0 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
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0x0001f0a4 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
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0x0001f0b8 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
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0x0001f0c0 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
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static const struct reg *reg_array[] = {
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[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
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[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
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[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
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[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
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[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
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[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
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[CH_C_QOS] = &reg_ch_c_qos,
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[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
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[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
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[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
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[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
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[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
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[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
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[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
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[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
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[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
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[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
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[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
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[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
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[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
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[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
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[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
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[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
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[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
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[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
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[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
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[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
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[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
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[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
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[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
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[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
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[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
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[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
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[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
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[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
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[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
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[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
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[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
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[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
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[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
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[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
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[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
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[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
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[CNTXT_INTSET] = &reg_cntxt_intset,
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[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
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};
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const struct regs gsi_regs_v3_5_1 = {
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.reg_count = ARRAY_SIZE(reg_array),
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.reg = reg_array,
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};

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