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LuBaolujoergroedel
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iommu/vt-d: Apply per pci device pasid table in SVA
This patch applies the per pci device pasid table in the Shared Virtual Address (SVA) implementation. Cc: Ashok Raj <[email protected]> Cc: Jacob Pan <[email protected]> Cc: Kevin Tian <[email protected]> Cc: Liu Yi L <[email protected]> Signed-off-by: Lu Baolu <[email protected]> Reviewed-by: Liu Yi L <[email protected]> Signed-off-by: Joerg Roedel <[email protected]>
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-32
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+19
-32
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drivers/iommu/intel-iommu.c

Lines changed: 9 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5178,22 +5178,16 @@ static void intel_iommu_put_resv_regions(struct device *dev,
51785178

51795179
#ifdef CONFIG_INTEL_IOMMU_SVM
51805180
#define MAX_NR_PASID_BITS (20)
5181-
static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)
5181+
static inline unsigned long intel_iommu_get_pts(struct device *dev)
51825182
{
5183-
/*
5184-
* Convert ecap_pss to extend context entry pts encoding, also
5185-
* respect the soft pasid_max value set by the iommu.
5186-
* - number of PASID bits = ecap_pss + 1
5187-
* - number of PASID table entries = 2^(pts + 5)
5188-
* Therefore, pts = ecap_pss - 4
5189-
* e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15
5190-
*/
5191-
if (ecap_pss(iommu->ecap) < 5)
5183+
int pts, max_pasid;
5184+
5185+
max_pasid = intel_pasid_get_dev_max_id(dev);
5186+
pts = find_first_bit((unsigned long *)&max_pasid, MAX_NR_PASID_BITS);
5187+
if (pts < 5)
51925188
return 0;
51935189

5194-
/* pasid_max is encoded as actual number of entries not the bits */
5195-
return find_first_bit((unsigned long *)&iommu->pasid_max,
5196-
MAX_NR_PASID_BITS) - 5;
5190+
return pts - 5;
51975191
}
51985192

51995193
int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev)
@@ -5229,8 +5223,8 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd
52295223
if (!(ctx_lo & CONTEXT_PASIDE)) {
52305224
if (iommu->pasid_state_table)
52315225
context[1].hi = (u64)virt_to_phys(iommu->pasid_state_table);
5232-
context[1].lo = (u64)virt_to_phys(iommu->pasid_table) |
5233-
intel_iommu_get_pts(iommu);
5226+
context[1].lo = (u64)virt_to_phys(info->pasid_table->table) |
5227+
intel_iommu_get_pts(sdev->dev);
52345228

52355229
wmb();
52365230
/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both
@@ -5297,11 +5291,6 @@ struct intel_iommu *intel_svm_device_to_iommu(struct device *dev)
52975291
return NULL;
52985292
}
52995293

5300-
if (!iommu->pasid_table) {
5301-
dev_err(dev, "PASID not enabled on IOMMU; cannot enable SVM\n");
5302-
return NULL;
5303-
}
5304-
53055294
return iommu;
53065295
}
53075296
#endif /* CONFIG_INTEL_IOMMU_SVM */

drivers/iommu/intel-svm.c

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -274,11 +274,9 @@ static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
274274
* page) so that we end up taking a fault that the hardware really
275275
* *has* to handle gracefully without affecting other processes.
276276
*/
277-
svm->iommu->pasid_table[svm->pasid].val = 0;
278-
wmb();
279-
280277
rcu_read_lock();
281278
list_for_each_entry_rcu(sdev, &svm->devs, list) {
279+
intel_pasid_clear_entry(sdev->dev, svm->pasid);
282280
intel_flush_pasid_dev(svm, sdev, svm->pasid);
283281
intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
284282
}
@@ -299,14 +297,15 @@ static LIST_HEAD(global_svm_list);
299297
int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
300298
{
301299
struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
300+
struct pasid_entry *entry;
302301
struct intel_svm_dev *sdev;
303302
struct intel_svm *svm = NULL;
304303
struct mm_struct *mm = NULL;
305304
u64 pasid_entry_val;
306305
int pasid_max;
307306
int ret;
308307

309-
if (!iommu || !iommu->pasid_table)
308+
if (!iommu)
310309
return -EINVAL;
311310

312311
if (dev_is_pci(dev)) {
@@ -384,8 +383,8 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
384383
}
385384
svm->iommu = iommu;
386385

387-
if (pasid_max > iommu->pasid_max)
388-
pasid_max = iommu->pasid_max;
386+
if (pasid_max > intel_pasid_max_id)
387+
pasid_max = intel_pasid_max_id;
389388

390389
/* Do not use PASID 0 in caching mode (virtualised IOMMU) */
391390
ret = intel_pasid_alloc_id(svm,
@@ -418,7 +417,8 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
418417
if (cpu_feature_enabled(X86_FEATURE_LA57))
419418
pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
420419

421-
iommu->pasid_table[svm->pasid].val = pasid_entry_val;
420+
entry = intel_pasid_get_entry(dev, svm->pasid);
421+
entry->val = pasid_entry_val;
422422

423423
wmb();
424424

@@ -453,7 +453,7 @@ int intel_svm_unbind_mm(struct device *dev, int pasid)
453453

454454
mutex_lock(&pasid_mutex);
455455
iommu = intel_svm_device_to_iommu(dev);
456-
if (!iommu || !iommu->pasid_table)
456+
if (!iommu)
457457
goto out;
458458

459459
svm = intel_pasid_lookup_id(pasid);
@@ -476,11 +476,9 @@ int intel_svm_unbind_mm(struct device *dev, int pasid)
476476
intel_flush_pasid_dev(svm, sdev, svm->pasid);
477477
intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
478478
kfree_rcu(sdev, rcu);
479+
intel_pasid_clear_entry(dev, svm->pasid);
479480

480481
if (list_empty(&svm->devs)) {
481-
svm->iommu->pasid_table[svm->pasid].val = 0;
482-
wmb();
483-
484482
intel_pasid_free_id(svm->pasid);
485483
if (svm->mm)
486484
mmu_notifier_unregister(&svm->notifier, svm->mm);
@@ -513,7 +511,7 @@ int intel_svm_is_pasid_valid(struct device *dev, int pasid)
513511

514512
mutex_lock(&pasid_mutex);
515513
iommu = intel_svm_device_to_iommu(dev);
516-
if (!iommu || !iommu->pasid_table)
514+
if (!iommu)
517515
goto out;
518516

519517
svm = intel_pasid_lookup_id(pasid);

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