@@ -102,20 +102,97 @@ static const struct regmap_irq_chip da9063_irq_chip = {
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.init_ack_masked = true,
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};
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+ static const struct regmap_irq da9063l_irqs [] = {
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+ /* DA9063 event A register */
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+ REGMAP_IRQ_REG (DA9063_IRQ_ONKEY ,
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+ DA9063_REG_EVENT_A_OFFSET , DA9063_M_ONKEY ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_ADC_RDY ,
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+ DA9063_REG_EVENT_A_OFFSET , DA9063_M_ADC_RDY ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_SEQ_RDY ,
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+ DA9063_REG_EVENT_A_OFFSET , DA9063_M_SEQ_RDY ),
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+ /* DA9063 event B register */
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+ REGMAP_IRQ_REG (DA9063_IRQ_WAKE ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_WAKE ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_TEMP ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_TEMP ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_COMP_1V2 ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_COMP_1V2 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_LDO_LIM ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_LDO_LIM ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_REG_UVOV ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_UVOV ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_DVC_RDY ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_DVC_RDY ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_VDD_MON ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_VDD_MON ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_WARN ,
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+ DA9063_REG_EVENT_B_OFFSET , DA9063_M_VDD_WARN ),
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+ /* DA9063 event C register */
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI0 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI0 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI1 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI1 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI2 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI2 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI3 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI3 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI4 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI4 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI5 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI5 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI6 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI6 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI7 ,
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+ DA9063_REG_EVENT_C_OFFSET , DA9063_M_GPI7 ),
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+ /* DA9063 event D register */
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI8 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI8 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI9 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI9 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI10 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI10 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI11 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI11 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI12 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI12 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI13 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI13 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI14 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI14 ),
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+ REGMAP_IRQ_REG (DA9063_IRQ_GPI15 ,
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+ DA9063_REG_EVENT_D_OFFSET , DA9063_M_GPI15 ),
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+ };
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+
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+ static const struct regmap_irq_chip da9063l_irq_chip = {
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+ .name = "da9063l-irq" ,
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+ .irqs = da9063l_irqs ,
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+ .num_irqs = ARRAY_SIZE (da9063l_irqs ),
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+ .num_regs = 4 ,
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+ .status_base = DA9063_REG_EVENT_A ,
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+ .mask_base = DA9063_REG_IRQ_MASK_A ,
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+ .ack_base = DA9063_REG_EVENT_A ,
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+ .init_ack_masked = true,
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+ };
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+
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int da9063_irq_init (struct da9063 * da9063 )
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{
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+ const struct regmap_irq_chip * irq_chip ;
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int ret ;
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if (!da9063 -> chip_irq ) {
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dev_err (da9063 -> dev , "No IRQ configured\n" );
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return - EINVAL ;
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}
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+ if (da9063 -> type == PMIC_TYPE_DA9063 )
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+ irq_chip = & da9063_irq_chip ;
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+ else
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+ irq_chip = & da9063l_irq_chip ;
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+
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ret = devm_regmap_add_irq_chip (da9063 -> dev , da9063 -> regmap ,
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da9063 -> chip_irq ,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED ,
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- da9063 -> irq_base , & da9063_irq_chip ,
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- & da9063 -> regmap_irq );
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+ da9063 -> irq_base , irq_chip , & da9063 -> regmap_irq );
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if (ret ) {
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dev_err (da9063 -> dev , "Failed to reguest IRQ %d: %d\n" ,
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da9063 -> chip_irq , ret );
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