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davem330davem330
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Merge branch 'pci-mrrs-consts'
Heiner Kallweit says: ==================== PCI: add two more values for PCIe Max_Read_Request_Size and initially use them in r8169 network driver In r8169 network driver I stumbled across a magic number translating to PCI MRRS size 4K. The PCI core is still missing constants for values 2K and 4K (as defined in PCI standard). So let's add these two constants and use the 4K constant in r8169. Second patch depends on the first one, therefore both patches preferrably should go through either PCI or netdev tree. ==================== Signed-off-by: David S. Miller <[email protected]>
2 parents 5da8baa + 8d98aa3 commit 4c85d2d

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-20
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2 files changed

+21
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‎drivers/net/ethernet/realtek/r8169.c

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,6 @@
8484
The RTL chips use a 64 element hash table based on the Ethernet CRC. */
8585
static const int multicast_filter_limit = 32;
8686

87-
#define MAX_READ_REQUEST_SHIFT 12
8887
#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
8988
#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
9089

@@ -5125,7 +5124,7 @@ static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
51255124
{
51265125
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
51275126
RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
5128-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5127+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
51295128
}
51305129

51315130
static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
@@ -5151,7 +5150,7 @@ static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
51515150
RTL_W8(tp, MaxTxPacketSize, 0x0c);
51525151
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
51535152
RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
5154-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5153+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
51555154
}
51565155

51575156
static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
@@ -5163,7 +5162,7 @@ static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
51635162
static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
51645163
{
51655164
rtl_tx_performance_tweak(tp,
5166-
(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5165+
PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
51675166
}
51685167

51695168
static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
@@ -5736,7 +5735,7 @@ static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
57365735
RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
57375736

57385737
if (tp->dev->mtu <= ETH_DATA_LEN) {
5739-
rtl_tx_performance_tweak(tp, (0x5 << MAX_READ_REQUEST_SHIFT) |
5738+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
57405739
PCI_EXP_DEVCTL_NOSNOOP_EN);
57415740
}
57425741
}
@@ -5757,7 +5756,7 @@ static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
57575756
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
57585757

57595758
if (tp->dev->mtu <= ETH_DATA_LEN)
5760-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5759+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
57615760

57625761
rtl_disable_clock_request(tp);
57635762

@@ -5788,7 +5787,7 @@ static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
57885787
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
57895788

57905789
if (tp->dev->mtu <= ETH_DATA_LEN)
5791-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5790+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
57925791

57935792
RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
57945793
}
@@ -5805,7 +5804,7 @@ static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
58055804
RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
58065805

58075806
if (tp->dev->mtu <= ETH_DATA_LEN)
5808-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5807+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
58095808

58105809
RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
58115810
}
@@ -5862,7 +5861,7 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp)
58625861
RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
58635862

58645863
if (tp->dev->mtu <= ETH_DATA_LEN)
5865-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5864+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
58665865

58675866
RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
58685867
}
@@ -5872,7 +5871,7 @@ static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
58725871
rtl_csi_access_enable_1(tp);
58735872

58745873
if (tp->dev->mtu <= ETH_DATA_LEN)
5875-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5874+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
58765875

58775876
RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
58785877

@@ -5889,7 +5888,7 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
58895888

58905889
rtl_csi_access_enable_1(tp);
58915890

5892-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5891+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
58935892

58945893
RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
58955894

@@ -5921,7 +5920,7 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
59215920
rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
59225921

59235922
if (tp->dev->mtu <= ETH_DATA_LEN)
5924-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5923+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
59255924

59265925
RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
59275926

@@ -5946,7 +5945,7 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
59465945
rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
59475946

59485947
if (tp->dev->mtu <= ETH_DATA_LEN)
5949-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5948+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
59505949

59515950
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
59525951
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
@@ -5976,7 +5975,7 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp)
59765975
{
59775976
rtl_csi_access_enable_2(tp);
59785977

5979-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5978+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
59805979

59815980
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
59825981
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
@@ -6047,7 +6046,7 @@ static void rtl_hw_start_8168g(struct rtl8169_private *tp)
60476046

60486047
rtl_csi_access_enable_1(tp);
60496048

6050-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6049+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
60516050

60526051
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
60536052
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
@@ -6147,7 +6146,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
61476146

61486147
rtl_csi_access_enable_1(tp);
61496148

6150-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6149+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
61516150

61526151
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
61536152
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
@@ -6229,7 +6228,7 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
62296228

62306229
rtl_csi_access_enable_1(tp);
62316230

6232-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6231+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
62336232

62346233
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
62356234
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
@@ -6495,7 +6494,7 @@ static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
64956494

64966495
RTL_W8(tp, DBG_REG, FIX_NAK_1);
64976496

6498-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6497+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
64996498

65006499
RTL_W8(tp, Config1,
65016500
LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
@@ -6512,7 +6511,7 @@ static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
65126511
{
65136512
rtl_csi_access_enable_2(tp);
65146513

6515-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6514+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
65166515

65176516
RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
65186517
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
@@ -6575,7 +6574,7 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp)
65756574

65766575
rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
65776576

6578-
rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6577+
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
65796578

65806579
rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
65816580
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);

‎include/uapi/linux/pci_regs.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -506,6 +506,8 @@
506506
#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
507507
#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
508508
#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
509+
#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
510+
#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
509511
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
510512
#define PCI_EXP_DEVSTA 10 /* Device Status */
511513
#define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */

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