@@ -57,7 +57,7 @@ struct gpio_bank {
57
57
u32 saved_datain ;
58
58
u32 level_mask ;
59
59
u32 toggle_mask ;
60
- spinlock_t lock ;
60
+ raw_spinlock_t lock ;
61
61
struct gpio_chip chip ;
62
62
struct clk * dbck ;
63
63
u32 mod_usage ;
@@ -498,17 +498,17 @@ static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
498
498
if (!BANK_USED (bank ))
499
499
pm_runtime_get_sync (bank -> dev );
500
500
501
- spin_lock_irqsave (& bank -> lock , flags );
501
+ raw_spin_lock_irqsave (& bank -> lock , flags );
502
502
retval = omap_set_gpio_triggering (bank , offset , type );
503
503
if (retval )
504
504
goto error ;
505
505
omap_gpio_init_irq (bank , offset );
506
506
if (!omap_gpio_is_input (bank , offset )) {
507
- spin_unlock_irqrestore (& bank -> lock , flags );
507
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
508
508
retval = - EINVAL ;
509
509
goto error ;
510
510
}
511
- spin_unlock_irqrestore (& bank -> lock , flags );
511
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
512
512
513
513
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH ))
514
514
irq_set_handler_locked (d , handle_level_irq );
@@ -634,14 +634,14 @@ static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
634
634
return - EINVAL ;
635
635
}
636
636
637
- spin_lock_irqsave (& bank -> lock , flags );
637
+ raw_spin_lock_irqsave (& bank -> lock , flags );
638
638
if (enable )
639
639
bank -> context .wake_en |= gpio_bit ;
640
640
else
641
641
bank -> context .wake_en &= ~gpio_bit ;
642
642
643
643
writel_relaxed (bank -> context .wake_en , bank -> base + bank -> regs -> wkup_en );
644
- spin_unlock_irqrestore (& bank -> lock , flags );
644
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
645
645
646
646
return 0 ;
647
647
}
@@ -667,10 +667,10 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
667
667
if (!BANK_USED (bank ))
668
668
pm_runtime_get_sync (bank -> dev );
669
669
670
- spin_lock_irqsave (& bank -> lock , flags );
670
+ raw_spin_lock_irqsave (& bank -> lock , flags );
671
671
omap_enable_gpio_module (bank , offset );
672
672
bank -> mod_usage |= BIT (offset );
673
- spin_unlock_irqrestore (& bank -> lock , flags );
673
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
674
674
675
675
return 0 ;
676
676
}
@@ -680,14 +680,14 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
680
680
struct gpio_bank * bank = container_of (chip , struct gpio_bank , chip );
681
681
unsigned long flags ;
682
682
683
- spin_lock_irqsave (& bank -> lock , flags );
683
+ raw_spin_lock_irqsave (& bank -> lock , flags );
684
684
bank -> mod_usage &= ~(BIT (offset ));
685
685
if (!LINE_USED (bank -> irq_usage , offset )) {
686
686
omap_set_gpio_direction (bank , offset , 1 );
687
687
omap_clear_gpio_debounce (bank , offset );
688
688
}
689
689
omap_disable_gpio_module (bank , offset );
690
- spin_unlock_irqrestore (& bank -> lock , flags );
690
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
691
691
692
692
/*
693
693
* If this is the last gpio to be freed in the bank,
@@ -789,7 +789,7 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
789
789
if (!BANK_USED (bank ))
790
790
pm_runtime_get_sync (bank -> dev );
791
791
792
- spin_lock_irqsave (& bank -> lock , flags );
792
+ raw_spin_lock_irqsave (& bank -> lock , flags );
793
793
794
794
if (!LINE_USED (bank -> mod_usage , offset ))
795
795
omap_set_gpio_direction (bank , offset , 1 );
@@ -798,12 +798,12 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
798
798
omap_enable_gpio_module (bank , offset );
799
799
bank -> irq_usage |= BIT (offset );
800
800
801
- spin_unlock_irqrestore (& bank -> lock , flags );
801
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
802
802
omap_gpio_unmask_irq (d );
803
803
804
804
return 0 ;
805
805
err :
806
- spin_unlock_irqrestore (& bank -> lock , flags );
806
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
807
807
if (!BANK_USED (bank ))
808
808
pm_runtime_put (bank -> dev );
809
809
return - EINVAL ;
@@ -815,15 +815,15 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
815
815
unsigned long flags ;
816
816
unsigned offset = d -> hwirq ;
817
817
818
- spin_lock_irqsave (& bank -> lock , flags );
818
+ raw_spin_lock_irqsave (& bank -> lock , flags );
819
819
bank -> irq_usage &= ~(BIT (offset ));
820
820
omap_set_gpio_irqenable (bank , offset , 0 );
821
821
omap_clear_gpio_irqstatus (bank , offset );
822
822
omap_set_gpio_triggering (bank , offset , IRQ_TYPE_NONE );
823
823
if (!LINE_USED (bank -> mod_usage , offset ))
824
824
omap_clear_gpio_debounce (bank , offset );
825
825
omap_disable_gpio_module (bank , offset );
826
- spin_unlock_irqrestore (& bank -> lock , flags );
826
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
827
827
828
828
/*
829
829
* If this is the last IRQ to be freed in the bank,
@@ -847,10 +847,10 @@ static void omap_gpio_mask_irq(struct irq_data *d)
847
847
unsigned offset = d -> hwirq ;
848
848
unsigned long flags ;
849
849
850
- spin_lock_irqsave (& bank -> lock , flags );
850
+ raw_spin_lock_irqsave (& bank -> lock , flags );
851
851
omap_set_gpio_irqenable (bank , offset , 0 );
852
852
omap_set_gpio_triggering (bank , offset , IRQ_TYPE_NONE );
853
- spin_unlock_irqrestore (& bank -> lock , flags );
853
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
854
854
}
855
855
856
856
static void omap_gpio_unmask_irq (struct irq_data * d )
@@ -860,7 +860,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
860
860
u32 trigger = irqd_get_trigger_type (d );
861
861
unsigned long flags ;
862
862
863
- spin_lock_irqsave (& bank -> lock , flags );
863
+ raw_spin_lock_irqsave (& bank -> lock , flags );
864
864
if (trigger )
865
865
omap_set_gpio_triggering (bank , offset , trigger );
866
866
@@ -872,7 +872,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
872
872
}
873
873
874
874
omap_set_gpio_irqenable (bank , offset , 1 );
875
- spin_unlock_irqrestore (& bank -> lock , flags );
875
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
876
876
}
877
877
878
878
/*---------------------------------------------------------------------*/
@@ -885,9 +885,9 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
885
885
OMAP_MPUIO_GPIO_MASKIT / bank -> stride ;
886
886
unsigned long flags ;
887
887
888
- spin_lock_irqsave (& bank -> lock , flags );
888
+ raw_spin_lock_irqsave (& bank -> lock , flags );
889
889
writel_relaxed (0xffff & ~bank -> context .wake_en , mask_reg );
890
- spin_unlock_irqrestore (& bank -> lock , flags );
890
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
891
891
892
892
return 0 ;
893
893
}
@@ -900,9 +900,9 @@ static int omap_mpuio_resume_noirq(struct device *dev)
900
900
OMAP_MPUIO_GPIO_MASKIT / bank -> stride ;
901
901
unsigned long flags ;
902
902
903
- spin_lock_irqsave (& bank -> lock , flags );
903
+ raw_spin_lock_irqsave (& bank -> lock , flags );
904
904
writel_relaxed (bank -> context .wake_en , mask_reg );
905
- spin_unlock_irqrestore (& bank -> lock , flags );
905
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
906
906
907
907
return 0 ;
908
908
}
@@ -948,9 +948,9 @@ static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
948
948
949
949
bank = container_of (chip , struct gpio_bank , chip );
950
950
reg = bank -> base + bank -> regs -> direction ;
951
- spin_lock_irqsave (& bank -> lock , flags );
951
+ raw_spin_lock_irqsave (& bank -> lock , flags );
952
952
dir = !!(readl_relaxed (reg ) & BIT (offset ));
953
- spin_unlock_irqrestore (& bank -> lock , flags );
953
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
954
954
return dir ;
955
955
}
956
956
@@ -960,9 +960,9 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
960
960
unsigned long flags ;
961
961
962
962
bank = container_of (chip , struct gpio_bank , chip );
963
- spin_lock_irqsave (& bank -> lock , flags );
963
+ raw_spin_lock_irqsave (& bank -> lock , flags );
964
964
omap_set_gpio_direction (bank , offset , 1 );
965
- spin_unlock_irqrestore (& bank -> lock , flags );
965
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
966
966
return 0 ;
967
967
}
968
968
@@ -984,10 +984,10 @@ static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
984
984
unsigned long flags ;
985
985
986
986
bank = container_of (chip , struct gpio_bank , chip );
987
- spin_lock_irqsave (& bank -> lock , flags );
987
+ raw_spin_lock_irqsave (& bank -> lock , flags );
988
988
bank -> set_dataout (bank , offset , value );
989
989
omap_set_gpio_direction (bank , offset , 0 );
990
- spin_unlock_irqrestore (& bank -> lock , flags );
990
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
991
991
return 0 ;
992
992
}
993
993
@@ -999,9 +999,9 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
999
999
1000
1000
bank = container_of (chip , struct gpio_bank , chip );
1001
1001
1002
- spin_lock_irqsave (& bank -> lock , flags );
1002
+ raw_spin_lock_irqsave (& bank -> lock , flags );
1003
1003
omap2_set_gpio_debounce (bank , offset , debounce );
1004
- spin_unlock_irqrestore (& bank -> lock , flags );
1004
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
1005
1005
1006
1006
return 0 ;
1007
1007
}
@@ -1012,9 +1012,9 @@ static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1012
1012
unsigned long flags ;
1013
1013
1014
1014
bank = container_of (chip , struct gpio_bank , chip );
1015
- spin_lock_irqsave (& bank -> lock , flags );
1015
+ raw_spin_lock_irqsave (& bank -> lock , flags );
1016
1016
bank -> set_dataout (bank , offset , value );
1017
- spin_unlock_irqrestore (& bank -> lock , flags );
1017
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
1018
1018
}
1019
1019
1020
1020
/*---------------------------------------------------------------------*/
@@ -1210,7 +1210,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
1210
1210
else
1211
1211
bank -> set_dataout = omap_set_gpio_dataout_mask ;
1212
1212
1213
- spin_lock_init (& bank -> lock );
1213
+ raw_spin_lock_init (& bank -> lock );
1214
1214
1215
1215
/* Static mapping, never released */
1216
1216
res = platform_get_resource (pdev , IORESOURCE_MEM , 0 );
@@ -1268,7 +1268,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1268
1268
unsigned long flags ;
1269
1269
u32 wake_low , wake_hi ;
1270
1270
1271
- spin_lock_irqsave (& bank -> lock , flags );
1271
+ raw_spin_lock_irqsave (& bank -> lock , flags );
1272
1272
1273
1273
/*
1274
1274
* Only edges can generate a wakeup event to the PRCM.
@@ -1321,7 +1321,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1321
1321
bank -> get_context_loss_count (bank -> dev );
1322
1322
1323
1323
omap_gpio_dbck_disable (bank );
1324
- spin_unlock_irqrestore (& bank -> lock , flags );
1324
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
1325
1325
1326
1326
return 0 ;
1327
1327
}
@@ -1336,7 +1336,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
1336
1336
unsigned long flags ;
1337
1337
int c ;
1338
1338
1339
- spin_lock_irqsave (& bank -> lock , flags );
1339
+ raw_spin_lock_irqsave (& bank -> lock , flags );
1340
1340
1341
1341
/*
1342
1342
* On the first resume during the probe, the context has not
@@ -1372,14 +1372,14 @@ static int omap_gpio_runtime_resume(struct device *dev)
1372
1372
if (c != bank -> context_loss_count ) {
1373
1373
omap_gpio_restore_context (bank );
1374
1374
} else {
1375
- spin_unlock_irqrestore (& bank -> lock , flags );
1375
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
1376
1376
return 0 ;
1377
1377
}
1378
1378
}
1379
1379
}
1380
1380
1381
1381
if (!bank -> workaround_enabled ) {
1382
- spin_unlock_irqrestore (& bank -> lock , flags );
1382
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
1383
1383
return 0 ;
1384
1384
}
1385
1385
@@ -1434,7 +1434,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
1434
1434
}
1435
1435
1436
1436
bank -> workaround_enabled = false;
1437
- spin_unlock_irqrestore (& bank -> lock , flags );
1437
+ raw_spin_unlock_irqrestore (& bank -> lock , flags );
1438
1438
1439
1439
return 0 ;
1440
1440
}
0 commit comments