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Merge tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas: - Add Tyrel Datwyler as maintainer for PPC64 RPA hotplug (Tyrel Datwyler) - Add Gustavo Pimentel as DesignWare PCI maintainer (Joao Pinto) - Fix a Switchtec Spectre v1 vulnerability (Gustavo A. R. Silva) - Revert an unnecessary Intel 300 ACS quirk (Mika Westerberg) - Fix pciehp hot-add/powerfault detection that left indicators in wrong state (Keith Busch) - Fix pci_reset_bus() logic error (Dennis Dalessandro) - Revert IB/hfi1 PCI reset change that caused a deadlock (Dennis Dalessandro) - Allow enabling PASID on Root Complex Integrated Endpoints (Felix Kuehling) * tag 'pci-v4.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: Fix enabling of PASID on RC integrated endpoints IB/hfi1,PCI: Allow bus reset while probing PCI: Fix faulty logic in pci_reset_bus() PCI: pciehp: Fix hot-add vs powerfault detection order switchtec: Fix Spectre v1 vulnerability Revert "PCI: Add ACS quirk for Intel 300 series" MAINTAINERS: Add Gustavo Pimentel as DesignWare PCI maintainer MAINTAINERS: Add entries for PPC64 RPA PCI hotplug drivers
2 parents d3bd597 + 9d27e39 commit 54eda9d

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‎MAINTAINERS

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7016,6 +7016,20 @@ F: drivers/crypto/vmx/aes*
70167016
F: drivers/crypto/vmx/ghash*
70177017
F: drivers/crypto/vmx/ppc-xlate.pl
70187018

7019+
IBM Power PCI Hotplug Driver for RPA-compliant PPC64 platform
7020+
M: Tyrel Datwyler <[email protected]>
7021+
L: [email protected]
7022+
L: [email protected]
7023+
S: Supported
7024+
F: drivers/pci/hotplug/rpaphp*
7025+
7026+
IBM Power IO DLPAR Driver for RPA-compliant PPC64 platform
7027+
M: Tyrel Datwyler <[email protected]>
7028+
L: [email protected]
7029+
L: [email protected]
7030+
S: Supported
7031+
F: drivers/pci/hotplug/rpadlpar*
7032+
70197033
IBM ServeRAID RAID DRIVER
70207034
S: Orphan
70217035
F: drivers/scsi/ips.*
@@ -11154,7 +11168,7 @@ F: drivers/pci/controller/dwc/pci-exynos.c
1115411168

1115511169
PCI DRIVER FOR SYNOPSYS DESIGNWARE
1115611170
M: Jingoo Han <[email protected]>
11157-
M: Joao Pinto <Joao.Pinto@synopsys.com>
11171+
M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
1115811172
L: [email protected]
1115911173
S: Maintained
1116011174
F: Documentation/devicetree/bindings/pci/designware-pcie.txt

‎drivers/infiniband/hw/hfi1/pcie.c

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd)
893893
}
894894

895895
/*
896-
* A secondary bus reset (SBR) issues a hot reset to our device.
897-
* The following routine does a 1s wait after the reset is dropped
898-
* per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
899-
* Conventional Reset, paragraph 3, line 35 also says that a 1s
900-
* delay after a reset is required. Per spec requirements,
901-
* the link is either working or not after that point.
896+
* This is an end around to do an SBR during probe time. A new API needs
897+
* to be implemented to have cleaner interface but this fixes the
898+
* current brokenness
902899
*/
903-
return pci_reset_bus(dev);
900+
return pci_bridge_secondary_bus_reset(dev->bus->self);
904901
}
905902

906903
/*

‎drivers/pci/hotplug/pciehp_hpc.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -496,7 +496,7 @@ int pciehp_power_on_slot(struct slot *slot)
496496
u16 slot_status;
497497
int retval;
498498

499-
/* Clear sticky power-fault bit from previous power failures */
499+
/* Clear power-fault bit from previous power failures */
500500
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
501501
if (slot_status & PCI_EXP_SLTSTA_PFD)
502502
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
@@ -646,6 +646,14 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
646646
pciehp_handle_button_press(slot);
647647
}
648648

649+
/* Check Power Fault Detected */
650+
if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
651+
ctrl->power_fault_detected = 1;
652+
ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
653+
pciehp_set_attention_status(slot, 1);
654+
pciehp_green_led_off(slot);
655+
}
656+
649657
/*
650658
* Disable requests have higher priority than Presence Detect Changed
651659
* or Data Link Layer State Changed events.
@@ -657,14 +665,6 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
657665
pciehp_handle_presence_or_link_change(slot, events);
658666
up_read(&ctrl->reset_lock);
659667

660-
/* Check Power Fault Detected */
661-
if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
662-
ctrl->power_fault_detected = 1;
663-
ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
664-
pciehp_set_attention_status(slot, 1);
665-
pciehp_green_led_off(slot);
666-
}
667-
668668
pci_config_pm_runtime_put(pdev);
669669
wake_up(&ctrl->requester);
670670
return IRQ_HANDLED;

‎drivers/pci/pci.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4547,6 +4547,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
45474547

45484548
return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
45494549
}
4550+
EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
45504551

45514552
static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
45524553
{
@@ -5200,7 +5201,7 @@ static int __pci_reset_bus(struct pci_bus *bus)
52005201
*/
52015202
int pci_reset_bus(struct pci_dev *pdev)
52025203
{
5203-
return pci_probe_reset_slot(pdev->slot) ?
5204+
return (!pci_probe_reset_slot(pdev->slot)) ?
52045205
__pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
52055206
}
52065207
EXPORT_SYMBOL_GPL(pci_reset_bus);

‎drivers/pci/probe.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2074,6 +2074,7 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
20742074
{
20752075
#ifdef CONFIG_PCI_PASID
20762076
struct pci_dev *bridge;
2077+
int pcie_type;
20772078
u32 cap;
20782079

20792080
if (!pci_is_pcie(dev))
@@ -2083,7 +2084,9 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
20832084
if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
20842085
return;
20852086

2086-
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2087+
pcie_type = pci_pcie_type(dev);
2088+
if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2089+
pcie_type == PCI_EXP_TYPE_RC_END)
20872090
dev->eetlp_prefix_path = 1;
20882091
else {
20892092
bridge = pci_upstream_bridge(dev);

‎drivers/pci/quirks.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4355,11 +4355,6 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
43554355
*
43564356
* 0x9d10-0x9d1b PCI Express Root port #{1-12}
43574357
*
4358-
* The 300 series chipset suffers from the same bug so include those root
4359-
* ports here as well.
4360-
*
4361-
* 0xa32c-0xa343 PCI Express Root port #{0-24}
4362-
*
43634358
* [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
43644359
* [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
43654360
* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
@@ -4377,7 +4372,6 @@ static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
43774372
case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
43784373
case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
43794374
case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4380-
case 0xa32c ... 0xa343: /* 300 series */
43814375
return true;
43824376
}
43834377

‎drivers/pci/switch/switchtec.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@
1414
#include <linux/poll.h>
1515
#include <linux/wait.h>
1616

17+
#include <linux/nospec.h>
18+
1719
MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
1820
MODULE_VERSION("0.1");
1921
MODULE_LICENSE("GPL");
@@ -909,6 +911,8 @@ static int ioctl_port_to_pff(struct switchtec_dev *stdev,
909911
default:
910912
if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id))
911913
return -EINVAL;
914+
p.port = array_index_nospec(p.port,
915+
ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1);
912916
p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]);
913917
break;
914918
}

‎include/linux/pci.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1235,6 +1235,9 @@ void pci_bus_remove_resources(struct pci_bus *bus);
12351235
int devm_request_pci_bus_resources(struct device *dev,
12361236
struct list_head *resources);
12371237

1238+
/* Temporary until new and working PCI SBR API in place */
1239+
int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1240+
12381241
#define pci_bus_for_each_resource(bus, res, i) \
12391242
for (i = 0; \
12401243
(res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \

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