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spi: sun6i: fix RX data corruption in DMA mode
Merge series from Tobias Schramm <[email protected]>: This set of patches fixes two bugs in the sun6i SPI driver that result in corruption of received data in DMA RX mode. The first bug seems to be related to an incompatibility of the SPI RX FIFO with wider than single byte read accesses during SPI transfers. I'm not sure if this bug affects all types of SPI controllers found in Allwinner SoCs supported by this driver. However reducing the access width should always be safe. I've tested this change on a V3s SoC. Further testing to narrow down the set of affected SoCs in the future would be welcome. The second bug is a race between SPI RX DMA and FIFO drain logic for interrupt-based SPI operation. This bug affects all SPI controllers supported by this driver. Once again this change has been tested on the Allwinner V3s SoC.
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‎.mailmap

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@@ -538,6 +538,8 @@ Shuah Khan <[email protected]> <[email protected]>
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Sibi Sankar <[email protected]> <[email protected]>
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Sid Manning <[email protected]> <[email protected]>
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Simon Arlott <[email protected]> <[email protected]>
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Simon Horman <[email protected]> <[email protected]>
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Simon Horman <[email protected]> <[email protected]>
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Simon Kelley <[email protected]>
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Sricharan Ramabadhran <[email protected]> <[email protected]>
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Srinivas Ramana <[email protected]> <[email protected]>

‎Documentation/ABI/testing/sysfs-class-led-trigger-netdev

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@@ -13,7 +13,7 @@ Description:
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Specifies the duration of the LED blink in milliseconds.
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Defaults to 50 ms.
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With hw_control ON, the interval value MUST be set to the
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When offloaded is true, the interval value MUST be set to the
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default value and cannot be changed.
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Trying to set any value in this specific mode will return
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an EINVAL error.
@@ -44,8 +44,8 @@ Description:
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If set to 1, the LED will blink for the milliseconds specified
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in interval to signal transmission.
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47-
With hw_control ON, the blink interval is controlled by hardware
48-
and won't reflect the value set in interval.
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When offloaded is true, the blink interval is controlled by
48+
hardware and won't reflect the value set in interval.
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What: /sys/class/leds/<led>/rx
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Date: Dec 2017
@@ -59,21 +59,21 @@ Description:
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If set to 1, the LED will blink for the milliseconds specified
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in interval to signal reception.
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With hw_control ON, the blink interval is controlled by hardware
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and won't reflect the value set in interval.
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When offloaded is true, the blink interval is controlled by
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hardware and won't reflect the value set in interval.
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What: /sys/class/leds/<led>/hw_control
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What: /sys/class/leds/<led>/offloaded
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Date: Jun 2023
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KernelVersion: 6.5
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Contact: [email protected]
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Description:
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Communicate whether the LED trigger modes are driven by hardware
71-
or software fallback is used.
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Communicate whether the LED trigger modes are offloaded to
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hardware or whether software fallback is used.
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If 0, the LED is using software fallback to blink.
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If 1, the LED is using hardware control to blink and signal the
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requested modes.
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If 1, the LED blinking in requested mode is offloaded to
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hardware.
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What: /sys/class/leds/<led>/link_10
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Date: Jun 2023

‎Documentation/admin-guide/hw-vuln/srso.rst

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@@ -141,8 +141,8 @@ sequence.
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To ensure the safety of this mitigation, the kernel must ensure that the
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safe return sequence is itself free from attacker interference. In Zen3
143143
and Zen4, this is accomplished by creating a BTB alias between the
144-
untraining function srso_untrain_ret_alias() and the safe return
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function srso_safe_ret_alias() which results in evicting a potentially
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untraining function srso_alias_untrain_ret() and the safe return
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function srso_alias_safe_ret() which results in evicting a potentially
146146
poisoned BTB entry and using that safe one for all function returns.
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In older Zen1 and Zen2, this is accomplished using a reinterpretation

‎Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml

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@@ -87,7 +87,7 @@ $defs:
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emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
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emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
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emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
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gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
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gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
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jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
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mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
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mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,

‎Documentation/i2c/writing-clients.rst

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@@ -46,7 +46,7 @@ driver model device node, and its I2C address.
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},
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.id_table = foo_idtable,
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.probe_new = foo_probe,
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.probe = foo_probe,
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.remove = foo_remove,
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/* if device autodetection is needed: */
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.class = I2C_CLASS_SOMETHING,

‎Documentation/networking/nf_conntrack-sysctl.rst

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@@ -178,10 +178,10 @@ nf_conntrack_sctp_timeout_established - INTEGER (seconds)
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Default is set to (hb_interval * path_max_retrans + rto_max)
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nf_conntrack_sctp_timeout_shutdown_sent - INTEGER (seconds)
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default 0.3
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default 3
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nf_conntrack_sctp_timeout_shutdown_recd - INTEGER (seconds)
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default 0.3
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default 3
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nf_conntrack_sctp_timeout_shutdown_ack_sent - INTEGER (seconds)
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default 3

‎MAINTAINERS

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@@ -8816,6 +8816,7 @@ R: Michael Walle <[email protected]>
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S: Maintained
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F: drivers/gpio/gpio-regmap.c
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F: include/linux/gpio/regmap.h
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K: (devm_)?gpio_regmap_(un)?register
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GPIO SUBSYSTEM
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M: Linus Walleij <[email protected]>
@@ -14816,6 +14817,16 @@ F: net/netfilter/xt_CONNSECMARK.c
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F: net/netfilter/xt_SECMARK.c
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F: net/netlabel/
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NETWORKING [MACSEC]
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M: Sabrina Dubroca <[email protected]>
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L: [email protected]
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S: Maintained
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F: drivers/net/macsec.c
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F: include/net/macsec.h
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F: include/uapi/linux/if_macsec.h
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K: macsec
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K: \bmdo_
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NETWORKING [MPTCP]
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M: Matthieu Baerts <[email protected]>
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M: Mat Martineau <[email protected]>
@@ -19237,13 +19248,6 @@ F: Documentation/devicetree/bindings/serial/serial.yaml
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F: drivers/tty/serdev/
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F: include/linux/serdev.h
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SERIAL DRIVERS
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M: Greg Kroah-Hartman <[email protected]>
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L: [email protected]
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S: Maintained
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F: Documentation/devicetree/bindings/serial/
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F: drivers/tty/serial/
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SERIAL IR RECEIVER
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M: Sean Young <[email protected]>
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L: [email protected]
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F: Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
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F: sound/soc/ti/
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TEXAS INSTRUMENTS AUDIO (ASoC/HDA) DRIVERS
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M: Shenghao Ding <[email protected]>
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M: Kevin Lu <[email protected]>
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M: Baojun Xu <[email protected]>
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/sound/tas2552.txt
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F: Documentation/devicetree/bindings/sound/tas2562.yaml
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F: Documentation/devicetree/bindings/sound/tas2770.yaml
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F: Documentation/devicetree/bindings/sound/tas27xx.yaml
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F: Documentation/devicetree/bindings/sound/ti,pcm1681.txt
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F: Documentation/devicetree/bindings/sound/ti,pcm3168a.yaml
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F: Documentation/devicetree/bindings/sound/ti,tlv320*.yaml
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F: Documentation/devicetree/bindings/sound/tlv320adcx140.yaml
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F: Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
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F: Documentation/devicetree/bindings/sound/tpa6130a2.txt
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F: include/sound/tas2*.h
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F: include/sound/tlv320*.h
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F: include/sound/tpa6130a2-plat.h
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F: sound/pci/hda/tas2781_hda_i2c.c
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F: sound/soc/codecs/pcm1681.c
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F: sound/soc/codecs/pcm1789*.*
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F: sound/soc/codecs/pcm179x*.*
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F: sound/soc/codecs/pcm186x*.*
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F: sound/soc/codecs/pcm3008.*
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F: sound/soc/codecs/pcm3060*.*
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F: sound/soc/codecs/pcm3168a*.*
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F: sound/soc/codecs/pcm5102a.c
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F: sound/soc/codecs/pcm512x*.*
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F: sound/soc/codecs/tas2*.*
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F: sound/soc/codecs/tlv320*.*
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F: sound/soc/codecs/tpa6130a2.*
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TEXAS INSTRUMENTS DMA DRIVERS
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M: Peter Ujfalusi <[email protected]>
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L: [email protected]
@@ -21648,20 +21685,16 @@ W: https://github.com/srcres258/linux-doc
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T: git git://github.com/srcres258/linux-doc.git doc-zh-tw
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F: Documentation/translations/zh_TW/
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21651-
TTY LAYER
21688+
TTY LAYER AND SERIAL DRIVERS
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M: Greg Kroah-Hartman <[email protected]>
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M: Jiri Slaby <[email protected]>
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L: [email protected]
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L: [email protected]
2165621693
S: Supported
2165721694
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git
21695+
F: Documentation/devicetree/bindings/serial/
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F: Documentation/driver-api/serial/
2165921697
F: drivers/tty/
21660-
F: drivers/tty/serial/serial_base.h
21661-
F: drivers/tty/serial/serial_base_bus.c
21662-
F: drivers/tty/serial/serial_core.c
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F: drivers/tty/serial/serial_ctrl.c
21664-
F: drivers/tty/serial/serial_port.c
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F: include/linux/selection.h
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F: include/linux/serial.h
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F: include/linux/serial_core.h
@@ -22488,7 +22521,6 @@ L: [email protected]
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S: Maintained
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F: drivers/block/virtio_blk.c
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F: drivers/scsi/virtio_scsi.c
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F: drivers/vhost/scsi.c
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F: include/uapi/linux/virtio_scsi.h
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F: include/uapi/linux/vhost.h
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F: kernel/vhost_task.c
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VIRTIO HOST (VHOST-SCSI)
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M: "Michael S. Tsirkin" <[email protected]>
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M: Jason Wang <[email protected]>
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M: Mike Christie <[email protected]>
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R: Paolo Bonzini <[email protected]>
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R: Stefan Hajnoczi <[email protected]>
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L: [email protected]
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S: Maintained
22630+
F: drivers/vhost/scsi.c
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2259022632
VIRTIO I2C DRIVER
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M: Viresh Kumar <[email protected]>

‎Makefile

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22
VERSION = 6
33
PATCHLEVEL = 5
44
SUBLEVEL = 0
5-
EXTRAVERSION = -rc6
5+
EXTRAVERSION =
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NAME = Hurr durr I'ma ninja sloth
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# *DOCUMENTATION*

‎arch/arm/boot/dts/arm/integratorap.dts

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158158
valid-mask = <0x003fffff>;
159159
};
160160

161-
pci: pciv3@62000000 {
161+
pci: pci@62000000 {
162162
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
163163
device_type = "pci";
164164
#interrupt-cells = <1>;

‎arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi

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182182
pinctrl-0 = <&pinctrl_rtc_int>;
183183
reg = <0x68>;
184184
interrupt-parent = <&gpio7>;
185-
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
185+
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
186186
status = "disabled";
187187
};
188188
};

‎arch/arm/boot/dts/nxp/imx/imx6sx.dtsi

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863863
reg = <0>;
864864

865865
ldb_from_lcdif1: endpoint {
866-
remote-endpoint = <&lcdif1_to_ldb>;
867866
};
868867
};
869868

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10101009
<&clks IMX6SX_CLK_USDHC1>;
10111010
clock-names = "ipg", "ahb", "per";
10121011
bus-width = <4>;
1012+
fsl,tuning-start-tap = <20>;
1013+
fsl,tuning-step= <2>;
10131014
status = "disabled";
10141015
};
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10221023
<&clks IMX6SX_CLK_USDHC2>;
10231024
clock-names = "ipg", "ahb", "per";
10241025
bus-width = <4>;
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fsl,tuning-start-tap = <20>;
1027+
fsl,tuning-step= <2>;
10251028
status = "disabled";
10261029
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10341037
<&clks IMX6SX_CLK_USDHC3>;
10351038
clock-names = "ipg", "ahb", "per";
10361039
bus-width = <4>;
1040+
fsl,tuning-start-tap = <20>;
1041+
fsl,tuning-step= <2>;
10371042
status = "disabled";
10381043
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13091314
power-domains = <&pd_disp>;
13101315
status = "disabled";
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1312-
ports {
1313-
port {
1314-
lcdif1_to_ldb: endpoint {
1315-
remote-endpoint = <&ldb_from_lcdif1>;
1316-
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1317+
port {
1318+
lcdif1_to_ldb: endpoint {
13171319
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‎arch/arm/boot/dts/nxp/imx/imx7s.dtsi

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11841184
<&clks IMX7D_USDHC1_ROOT_CLK>;
11851185
clock-names = "ipg", "ahb", "per";
11861186
bus-width = <4>;
1187+
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1188+
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11871189
status = "disabled";
11881190
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11961198
<&clks IMX7D_USDHC2_ROOT_CLK>;
11971199
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1201+
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1202+
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status = "disabled";
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12081212
<&clks IMX7D_USDHC3_ROOT_CLK>;
12091213
clock-names = "ipg", "ahb", "per";
12101214
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1215+
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1216+
fsl,tuning-start-tap = <20>;
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status = "disabled";
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‎arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi

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Original file line numberDiff line numberDiff line change
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145145
/* MDIO */
146146
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
147147
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
148+
/* Added to support GPIO controlled PHY reset */
149+
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7)
148150
>;
149151
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153155
/* MDIO reset value */
154156
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
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AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
158+
/* Added to support GPIO controlled PHY reset */
159+
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
156160
>;
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};
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215219
baseboard_eeprom: baseboard_eeprom@50 {
216220
compatible = "atmel,24c256";
217221
reg = <0x50>;
222+
vcc-supply = <&ldo4_reg>;
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219224
#address-cells = <1>;
220225
#size-cells = <1>;
@@ -377,6 +382,10 @@
377382

378383
ethphy0: ethernet-phy@0 {
379384
reg = <0>;
385+
/* Support GPIO reset on revision C3 boards */
386+
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
387+
reset-assert-us = <300>;
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reset-deassert-us = <6500>;
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};
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‎arch/arm/mach-zynq/pm.c

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*/
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#include <linux/io.h>
11+
#include <linux/of.h>
1112
#include <linux/of_address.h>
12-
#include <linux/of_device.h>
1313
#include "common.h"
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/* register offsets */

‎arch/arm64/boot/dts/freescale/imx8mm.dtsi

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compatible = "fsl,imx8mm-mipi-csi2";
12221222
reg = <0x32e30000 0x1000>;
12231223
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1224-
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1225-
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
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<&clk IMX8MM_SYS_PLL2_1000M>;
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assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
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clock-frequency = <333000000>;
12291228
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
12301229
<&clk IMX8MM_CLK_CSI1_ROOT>,

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