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lisheng011
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net: hns: add support of pause frame ctrl for HNS V2
The patch adds support of pause ctrl for HNS V2, and this feature is lost by HNS V1: 1) service ports can disable rx pause frame, 2) debug ports can open tx/rx pause frame. And this patch updates the REGs about the pause ctrl when updated status function called by upper layer routine. Signed-off-by: Lisheng <[email protected]> Signed-off-by: Yisen Zhuang <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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6 files changed

+104
-38
lines changed

6 files changed

+104
-38
lines changed

‎drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -399,11 +399,16 @@ static void hns_ae_get_ring_bdnum_limit(struct hnae_queue *queue,
399399
static void hns_ae_get_pauseparam(struct hnae_handle *handle,
400400
u32 *auto_neg, u32 *rx_en, u32 *tx_en)
401401
{
402-
assert(handle);
402+
struct hns_mac_cb *mac_cb = hns_get_mac_cb(handle);
403+
struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
403404

404-
hns_mac_get_autoneg(hns_get_mac_cb(handle), auto_neg);
405+
hns_mac_get_autoneg(mac_cb, auto_neg);
405406

406-
hns_mac_get_pauseparam(hns_get_mac_cb(handle), rx_en, tx_en);
407+
hns_mac_get_pauseparam(mac_cb, rx_en, tx_en);
408+
409+
/* Service port's pause feature is provided by DSAF, not mac */
410+
if (handle->port_type == HNAE_PORT_SERVICE)
411+
hns_dsaf_get_rx_mac_pause_en(dsaf_dev, mac_cb->mac_id, rx_en);
407412
}
408413

409414
static int hns_ae_set_autoneg(struct hnae_handle *handle, u8 enable)
@@ -436,12 +441,21 @@ static int hns_ae_set_pauseparam(struct hnae_handle *handle,
436441
u32 autoneg, u32 rx_en, u32 tx_en)
437442
{
438443
struct hns_mac_cb *mac_cb = hns_get_mac_cb(handle);
444+
struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
439445
int ret;
440446

441447
ret = hns_mac_set_autoneg(mac_cb, autoneg);
442448
if (ret)
443449
return ret;
444450

451+
/* Service port's pause feature is provided by DSAF, not mac */
452+
if (handle->port_type == HNAE_PORT_SERVICE) {
453+
ret = hns_dsaf_set_rx_mac_pause_en(dsaf_dev,
454+
mac_cb->mac_id, rx_en);
455+
if (ret)
456+
return ret;
457+
rx_en = 0;
458+
}
445459
return hns_mac_set_pauseparam(mac_cb, rx_en, tx_en);
446460
}
447461

‎drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c

Lines changed: 7 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -439,9 +439,8 @@ int hns_mac_vm_config_bc_en(struct hns_mac_cb *mac_cb, u32 vmid, bool enable)
439439

440440
void hns_mac_reset(struct hns_mac_cb *mac_cb)
441441
{
442-
struct mac_driver *drv;
443-
444-
drv = hns_mac_get_drv(mac_cb);
442+
struct mac_driver *drv = hns_mac_get_drv(mac_cb);
443+
bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
445444

446445
drv->mac_init(drv);
447446

@@ -456,7 +455,7 @@ void hns_mac_reset(struct hns_mac_cb *mac_cb)
456455

457456
if (drv->mac_pausefrm_cfg) {
458457
if (mac_cb->mac_type == HNAE_PORT_DEBUG)
459-
drv->mac_pausefrm_cfg(drv, 0, 0);
458+
drv->mac_pausefrm_cfg(drv, !is_ver1, !is_ver1);
460459
else /* mac rx must disable, dsaf pfc close instead of it*/
461460
drv->mac_pausefrm_cfg(drv, 0, 1);
462461
}
@@ -561,14 +560,6 @@ void hns_mac_get_pauseparam(struct hns_mac_cb *mac_cb, u32 *rx_en, u32 *tx_en)
561560
*rx_en = 0;
562561
*tx_en = 0;
563562
}
564-
565-
/* Due to the chip defect, the service mac's rx pause CAN'T be enabled.
566-
* We set the rx pause frm always be true (1), because DSAF deals with
567-
* the rx pause frm instead of service mac. After all, we still support
568-
* rx pause frm.
569-
*/
570-
if (mac_cb->mac_type == HNAE_PORT_SERVICE)
571-
*rx_en = 1;
572563
}
573564

574565
/**
@@ -602,20 +593,13 @@ int hns_mac_set_autoneg(struct hns_mac_cb *mac_cb, u8 enable)
602593
int hns_mac_set_pauseparam(struct hns_mac_cb *mac_cb, u32 rx_en, u32 tx_en)
603594
{
604595
struct mac_driver *mac_ctrl_drv = hns_mac_get_drv(mac_cb);
596+
bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
605597

606-
if (mac_cb->mac_type == HNAE_PORT_SERVICE) {
607-
if (!rx_en) {
608-
dev_err(mac_cb->dev, "disable rx_pause is not allowed!");
598+
if (mac_cb->mac_type == HNAE_PORT_DEBUG) {
599+
if (is_ver1 && (tx_en || rx_en)) {
600+
dev_err(mac_cb->dev, "macv1 cann't enable tx/rx_pause!");
609601
return -EINVAL;
610602
}
611-
} else if (mac_cb->mac_type == HNAE_PORT_DEBUG) {
612-
if (tx_en || rx_en) {
613-
dev_err(mac_cb->dev, "enable tx_pause or enable rx_pause are not allowed!");
614-
return -EINVAL;
615-
}
616-
} else {
617-
dev_err(mac_cb->dev, "Unsupport this operation!");
618-
return -EINVAL;
619603
}
620604

621605
if (mac_ctrl_drv->mac_pausefrm_cfg)

‎drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

Lines changed: 65 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1022,12 +1022,52 @@ static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
10221022
* @mac_cb: mac contrl block
10231023
*/
10241024
static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1025-
int mac_id, int en)
1025+
int mac_id, int tc_en)
10261026
{
1027-
if (!en)
1028-
dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, 0);
1027+
dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1028+
}
1029+
1030+
static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1031+
int mac_id, int tx_en, int rx_en)
1032+
{
1033+
if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1034+
if (!tx_en || !rx_en)
1035+
dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1036+
1037+
return;
1038+
}
1039+
1040+
dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1041+
DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1042+
dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1043+
DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1044+
}
1045+
1046+
int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1047+
u32 en)
1048+
{
1049+
if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1050+
if (!en)
1051+
dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1052+
1053+
return -EINVAL;
1054+
}
1055+
1056+
dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1057+
DSAF_MAC_PAUSE_RX_EN_B, !!en);
1058+
1059+
return 0;
1060+
}
1061+
1062+
void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1063+
u32 *en)
1064+
{
1065+
if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1066+
*en = 1;
10291067
else
1030-
dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, 0xff);
1068+
*en = dsaf_get_dev_bit(dsaf_dev,
1069+
DSAF_PAUSE_CFG_REG + mac_id * 4,
1070+
DSAF_MAC_PAUSE_RX_EN_B);
10311071
}
10321072

10331073
/**
@@ -1039,6 +1079,7 @@ static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
10391079
{
10401080
u32 i;
10411081
u32 o_dsaf_cfg;
1082+
bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
10421083

10431084
o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
10441085
dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
@@ -1064,8 +1105,10 @@ static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
10641105
hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
10651106

10661107
/*set dsaf pfc to 0 for parseing rx pause*/
1067-
for (i = 0; i < DSAF_COMM_CHN; i++)
1108+
for (i = 0; i < DSAF_COMM_CHN; i++) {
10681109
hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1110+
hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1111+
}
10691112

10701113
/*msk and clr exception irqs */
10711114
for (i = 0; i < DSAF_COMM_CHN; i++) {
@@ -2013,6 +2056,8 @@ void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
20132056
{
20142057
struct dsaf_hw_stats *hw_stats
20152058
= &dsaf_dev->hw_stats[node_num];
2059+
bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2060+
u32 reg_tmp;
20162061

20172062
hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
20182063
DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
@@ -2022,8 +2067,12 @@ void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
20222067
DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
20232068
hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
20242069
DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2025-
hw_stats->rx_pause_frame += dsaf_read_dev(dsaf_dev,
2026-
DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG + 0x80 * (u64)node_num);
2070+
2071+
reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2072+
DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2073+
hw_stats->rx_pause_frame +=
2074+
dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2075+
20272076
hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
20282077
DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
20292078
hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
@@ -2056,6 +2105,8 @@ void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
20562105
u32 i = 0;
20572106
u32 j;
20582107
u32 *p = data;
2108+
u32 reg_tmp;
2109+
bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
20592110

20602111
/* dsaf common registers */
20612112
p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
@@ -2120,8 +2171,9 @@ void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
21202171
DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
21212172
p[190 + i] = dsaf_read_dev(ddev,
21222173
DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2123-
p[193 + i] = dsaf_read_dev(ddev,
2124-
DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG + j * 0x80);
2174+
reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2175+
DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2176+
p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
21252177
p[196 + i] = dsaf_read_dev(ddev,
21262178
DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
21272179
p[199 + i] = dsaf_read_dev(ddev,
@@ -2368,8 +2420,11 @@ void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
23682420
p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
23692421
p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
23702422

2423+
if (!is_ver1)
2424+
p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2425+
23712426
/* mark end of dsaf regs */
2372-
for (i = 498; i < 504; i++)
2427+
for (i = 499; i < 504; i++)
23732428
p[i] = 0xdddddddd;
23742429
}
23752430

‎drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -417,6 +417,11 @@ void hns_dsaf_get_strings(int stringset, u8 *data, int port);
417417
void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
418418
int hns_dsaf_get_regs_count(void);
419419
void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
420+
421+
void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
422+
u32 *en);
423+
int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
424+
u32 en);
420425
void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en);
421426

422427
#endif /* __HNS_DSAF_MAIN_H__ */

‎drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -332,10 +332,12 @@ static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
332332
/* clr and msk except irq*/
333333
hns_ppe_exc_irq_en(ppe_cb, 0);
334334

335-
if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG)
335+
if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
336336
hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
337-
else
337+
dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
338+
} else {
338339
hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
340+
}
339341

340342
hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
341343
hns_ppe_cnt_clr_ce(ppe_cb);

‎drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,7 @@
137137
#define DSAF_PPE_INT_STS_0_REG 0x1E0
138138
#define DSAF_ROCEE_INT_STS_0_REG 0x200
139139
#define DSAFV2_SERDES_LBK_0_REG 0x220
140+
#define DSAF_PAUSE_CFG_REG 0x240
140141
#define DSAF_PPE_QID_CFG_0_REG 0x300
141142
#define DSAF_SW_PORT_TYPE_0_REG 0x320
142143
#define DSAF_STP_PORT_TYPE_0_REG 0x340
@@ -155,6 +156,7 @@
155156
#define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG 0x1030
156157
#define DSAF_INODE_SBM_PID_NUM_0_REG 0x1038
157158
#define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x103C
159+
#define DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x1024
158160
#define DSAF_INODE_SBM_RELS_NUM_0_REG 0x104C
159161
#define DSAF_INODE_SBM_DROP_NUM_0_REG 0x1050
160162
#define DSAF_INODE_CRC_FALSE_NUM_0_REG 0x1054
@@ -711,6 +713,10 @@
711713
#define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1)
712714
#define DSAF_PFC_UNINT_CNT_S 0
713715

716+
#define DSAF_MAC_PAUSE_RX_EN_B 2
717+
#define DSAF_PFC_PAUSE_RX_EN_B 1
718+
#define DSAF_PFC_PAUSE_TX_EN_B 0
719+
714720
#define DSAF_PPE_QID_CFG_M 0xFF
715721
#define DSAF_PPE_QID_CFG_S 0
716722

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