@@ -5061,32 +5061,27 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
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struct drm_device * dev = dev_priv -> dev ;
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u32 val , rp0 ;
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- if (dev -> pdev -> revision >= 0x20 ) {
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- val = vlv_punit_read (dev_priv , FB_GFX_FMAX_AT_VMAX_FUSE );
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+ val = vlv_punit_read (dev_priv , FB_GFX_FMAX_AT_VMAX_FUSE );
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- switch (INTEL_INFO (dev )-> eu_total ) {
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- case 8 :
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- /* (2 * 4) config */
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- rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT );
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- break ;
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- case 12 :
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- /* (2 * 6) config */
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- rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT );
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- break ;
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- case 16 :
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- /* (2 * 8) config */
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- default :
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- /* Setting (2 * 8) Min RP0 for any other combination */
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- rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );
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- break ;
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- }
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- rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK );
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- } else {
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- /* For pre-production hardware */
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- val = vlv_punit_read (dev_priv , PUNIT_GPU_STATUS_REG );
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- rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &
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- PUNIT_GPU_STATUS_MAX_FREQ_MASK ;
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+ switch (INTEL_INFO (dev )-> eu_total ) {
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+ case 8 :
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+ /* (2 * 4) config */
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+ rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT );
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+ break ;
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+ case 12 :
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+ /* (2 * 6) config */
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+ rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT );
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+ break ;
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+ case 16 :
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+ /* (2 * 8) config */
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+ default :
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+ /* Setting (2 * 8) Min RP0 for any other combination */
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+ rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );
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+ break ;
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}
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+
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+ rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK );
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+
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return rp0 ;
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}
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@@ -5102,18 +5097,11 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
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static int cherryview_rps_guar_freq (struct drm_i915_private * dev_priv )
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{
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- struct drm_device * dev = dev_priv -> dev ;
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u32 val , rp1 ;
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- if (dev -> pdev -> revision >= 0x20 ) {
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- val = vlv_punit_read (dev_priv , FB_GFX_FMAX_AT_VMAX_FUSE );
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- rp1 = (val & FB_GFX_FREQ_FUSE_MASK );
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- } else {
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- /* For pre-production hardware */
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- val = vlv_punit_read (dev_priv , PUNIT_REG_GPU_FREQ_STS );
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- rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &
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- PUNIT_GPU_STATUS_MAX_FREQ_MASK );
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- }
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+ val = vlv_punit_read (dev_priv , FB_GFX_FMAX_AT_VMAX_FUSE );
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+ rp1 = (val & FB_GFX_FREQ_FUSE_MASK );
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+
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return rp1 ;
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}
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