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jnikuladanvet
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drm/i915/chv: remove pre-production hardware workarounds
Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> [danvet: Appease gcc and remove the unused variable.] Signed-off-by: Daniel Vetter <[email protected]>
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drivers/gpu/drm/i915/intel_pm.c

Lines changed: 22 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -5061,32 +5061,27 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
50615061
struct drm_device *dev = dev_priv->dev;
50625062
u32 val, rp0;
50635063

5064-
if (dev->pdev->revision >= 0x20) {
5065-
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5064+
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
50665065

5067-
switch (INTEL_INFO(dev)->eu_total) {
5068-
case 8:
5069-
/* (2 * 4) config */
5070-
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5071-
break;
5072-
case 12:
5073-
/* (2 * 6) config */
5074-
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5075-
break;
5076-
case 16:
5077-
/* (2 * 8) config */
5078-
default:
5079-
/* Setting (2 * 8) Min RP0 for any other combination */
5080-
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5081-
break;
5082-
}
5083-
rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5084-
} else {
5085-
/* For pre-production hardware */
5086-
val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5087-
rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5088-
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5066+
switch (INTEL_INFO(dev)->eu_total) {
5067+
case 8:
5068+
/* (2 * 4) config */
5069+
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5070+
break;
5071+
case 12:
5072+
/* (2 * 6) config */
5073+
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5074+
break;
5075+
case 16:
5076+
/* (2 * 8) config */
5077+
default:
5078+
/* Setting (2 * 8) Min RP0 for any other combination */
5079+
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5080+
break;
50895081
}
5082+
5083+
rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5084+
50905085
return rp0;
50915086
}
50925087

@@ -5102,18 +5097,11 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
51025097

51035098
static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
51045099
{
5105-
struct drm_device *dev = dev_priv->dev;
51065100
u32 val, rp1;
51075101

5108-
if (dev->pdev->revision >= 0x20) {
5109-
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5110-
rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5111-
} else {
5112-
/* For pre-production hardware */
5113-
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5114-
rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5115-
PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5116-
}
5102+
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5103+
rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5104+
51175105
return rp1;
51185106
}
51195107

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