Skip to content

Commit 5e3bf9c

Browse files
Chunfeng Yunkishon
authored andcommitted
dt-bindings: phy-mt65xx-usb: add support for new version phy
add a new compatible string for "mt2712", and move reference clock into each port node; Signed-off-by: Chunfeng Yun <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
1 parent c0250fe commit 5e3bf9c

File tree

1 file changed

+80
-13
lines changed

1 file changed

+80
-13
lines changed

Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt

Lines changed: 80 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -6,21 +6,31 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
66
Required properties (controller (parent) node):
77
- compatible : should be one of
88
"mediatek,mt2701-u3phy"
9+
"mediatek,mt2712-u3phy"
910
"mediatek,mt8173-u3phy"
10-
- reg : offset and length of register for phy, exclude port's
11-
register.
12-
- clocks : a list of phandle + clock-specifier pairs, one for each
13-
entry in clock-names
14-
- clock-names : must contain
11+
- clocks : (deprecated, use port's clocks instead) a list of phandle +
12+
clock-specifier pairs, one for each entry in clock-names
13+
- clock-names : (deprecated, use port's one instead) must contain
1514
"u3phya_ref": for reference clock of usb3.0 analog phy.
1615

1716
Required nodes : a sub-node is required for each port the controller
1817
provides. Address range information including the usual
1918
'reg' property is used inside these nodes to describe
2019
the controller's topology.
2120

21+
Optional properties (controller (parent) node):
22+
- reg : offset and length of register shared by multiple ports,
23+
exclude port's private register. It is needed on mt2701
24+
and mt8173, but not on mt2712.
25+
2226
Required properties (port (child) node):
2327
- reg : address and length of the register set for the port.
28+
- clocks : a list of phandle + clock-specifier pairs, one for each
29+
entry in clock-names
30+
- clock-names : must contain
31+
"ref": 48M reference clock for HighSpeed analog phy; and 26M
32+
reference clock for SuperSpeed analog phy, sometimes is
33+
24M, 25M or 27M, depended on platform.
2434
- #phy-cells : should be 1 (See second example)
2535
cell after port phandle is phy type from:
2636
- PHY_TYPE_USB2
@@ -31,21 +41,31 @@ Example:
3141
u3phy: usb-phy@11290000 {
3242
compatible = "mediatek,mt8173-u3phy";
3343
reg = <0 0x11290000 0 0x800>;
34-
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
35-
clock-names = "u3phya_ref";
3644
#address-cells = <2>;
3745
#size-cells = <2>;
3846
ranges;
3947
status = "okay";
4048

41-
phy_port0: port@11290800 {
42-
reg = <0 0x11290800 0 0x800>;
49+
u2port0: usb-phy@11290800 {
50+
reg = <0 0x11290800 0 0x100>;
51+
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
52+
clock-names = "ref";
4353
#phy-cells = <1>;
4454
status = "okay";
4555
};
4656

47-
phy_port1: port@11291000 {
48-
reg = <0 0x11291000 0 0x800>;
57+
u3port0: usb-phy@11290900 {
58+
reg = <0 0x11290800 0 0x700>;
59+
clocks = <&clk26m>;
60+
clock-names = "ref";
61+
#phy-cells = <1>;
62+
status = "okay";
63+
};
64+
65+
u2port1: usb-phy@11291000 {
66+
reg = <0 0x11291000 0 0x100>;
67+
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
68+
clock-names = "ref";
4969
#phy-cells = <1>;
5070
status = "okay";
5171
};
@@ -64,7 +84,54 @@ Example:
6484

6585
usb30: usb@11270000 {
6686
...
67-
phys = <&phy_port0 PHY_TYPE_USB3>;
68-
phy-names = "usb3-0";
87+
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
88+
phy-names = "usb2-0", "usb3-0";
6989
...
7090
};
91+
92+
93+
Layout differences of banks between mt8173/mt2701 and mt2712
94+
-------------------------------------------------------------
95+
mt8173 and mt2701:
96+
port offset bank
97+
shared 0x0000 SPLLC
98+
0x0100 FMREG
99+
u2 port0 0x0800 U2PHY_COM
100+
u3 port0 0x0900 U3PHYD
101+
0x0a00 U3PHYD_BANK2
102+
0x0b00 U3PHYA
103+
0x0c00 U3PHYA_DA
104+
u2 port1 0x1000 U2PHY_COM
105+
u3 port1 0x1100 U3PHYD
106+
0x1200 U3PHYD_BANK2
107+
0x1300 U3PHYA
108+
0x1400 U3PHYA_DA
109+
u2 port2 0x1800 U2PHY_COM
110+
...
111+
112+
mt2712:
113+
port offset bank
114+
u2 port0 0x0000 MISC
115+
0x0100 FMREG
116+
0x0300 U2PHY_COM
117+
u3 port0 0x0700 SPLLC
118+
0x0800 CHIP
119+
0x0900 U3PHYD
120+
0x0a00 U3PHYD_BANK2
121+
0x0b00 U3PHYA
122+
0x0c00 U3PHYA_DA
123+
u2 port1 0x1000 MISC
124+
0x1100 FMREG
125+
0x1300 U2PHY_COM
126+
u3 port1 0x1700 SPLLC
127+
0x1800 CHIP
128+
0x1900 U3PHYD
129+
0x1a00 U3PHYD_BANK2
130+
0x1b00 U3PHYA
131+
0x1c00 U3PHYA_DA
132+
u2 port2 0x2000 MISC
133+
...
134+
135+
SPLLC shared by u3 ports and FMREG shared by u2 ports on
136+
mt8173/mt2701 are put back into each port; a new bank MISC for
137+
u2 ports and CHIP for u3 ports are added on mt2712.

0 commit comments

Comments
 (0)