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Yixian Liujgunthorpe
Yixian Liu
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jgunthorpe
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RDMA/hns: Add 64KB page size support for hip08
This patch adds the support of 64KB page size for hip08 in kernel. Signed-off-by: Yixian Liu <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]>
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+23
-22
lines changed

3 files changed

+23
-22
lines changed

‎drivers/infiniband/hw/hns/hns_roce_device.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,9 @@
100100
#define SERV_TYPE_UC 2
101101
#define SERV_TYPE_UD 3
102102

103+
/* Configure to HW for PAGE_SIZE larger than 4KB */
104+
#define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
105+
103106
#define PAGES_SHIFT_8 8
104107
#define PAGES_SHIFT_16 16
105108
#define PAGES_SHIFT_24 24

‎drivers/infiniband/hw/hns/hns_roce_hw_v2.c

Lines changed: 20 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1024,40 +1024,40 @@ static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
10241024

10251025
roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
10261026
CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
1027-
hr_dev->caps.qpc_ba_pg_sz);
1027+
hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
10281028
roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
10291029
CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
1030-
hr_dev->caps.qpc_buf_pg_sz);
1030+
hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
10311031
roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
10321032
CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
10331033
qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
10341034

10351035
roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
10361036
CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
1037-
hr_dev->caps.srqc_ba_pg_sz);
1037+
hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
10381038
roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
10391039
CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
1040-
hr_dev->caps.srqc_buf_pg_sz);
1040+
hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
10411041
roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
10421042
CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
10431043
srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
10441044

10451045
roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
10461046
CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
1047-
hr_dev->caps.cqc_ba_pg_sz);
1047+
hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
10481048
roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
10491049
CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
1050-
hr_dev->caps.cqc_buf_pg_sz);
1050+
hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
10511051
roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
10521052
CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
10531053
cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
10541054

10551055
roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
10561056
CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
1057-
hr_dev->caps.mpt_ba_pg_sz);
1057+
hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
10581058
roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
10591059
CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
1060-
hr_dev->caps.mpt_buf_pg_sz);
1060+
hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
10611061
roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
10621062
CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
10631063
mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
@@ -1351,7 +1351,8 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
13511351
HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
13521352
roce_set_field(mpt_entry->byte_4_pd_hop_st,
13531353
V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1354-
V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz);
1354+
V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1355+
mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
13551356
roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
13561357
V2_MPT_BYTE_4_PD_S, mr->pd);
13571358
mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
@@ -1425,7 +1426,8 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
14251426

14261427
roce_set_field(mpt_entry->byte_64_buf_pa1,
14271428
V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1428-
V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz);
1429+
V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1430+
mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
14291431
mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
14301432

14311433
return 0;
@@ -1606,11 +1608,11 @@ static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
16061608
roce_set_field(cq_context->byte_24_pgsz_addr,
16071609
V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
16081610
V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
1609-
hr_dev->caps.cqe_ba_pg_sz);
1611+
hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
16101612
roce_set_field(cq_context->byte_24_pgsz_addr,
16111613
V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
16121614
V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
1613-
hr_dev->caps.cqe_buf_pg_sz);
1615+
hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
16141616

16151617
cq_context->cqe_ba = (u32)(dma_handle >> 3);
16161618

@@ -2707,15 +2709,15 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
27072709
roce_set_field(context->byte_16_buf_ba_pg_sz,
27082710
V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
27092711
V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
2710-
hr_dev->caps.mtt_ba_pg_sz);
2712+
hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
27112713
roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
27122714
V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
27132715
V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
27142716

27152717
roce_set_field(context->byte_16_buf_ba_pg_sz,
27162718
V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
27172719
V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
2718-
hr_dev->caps.mtt_buf_pg_sz);
2720+
hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
27192721
roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
27202722
V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
27212723
V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
@@ -4149,12 +4151,14 @@ static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
41494151
/* set eqe_ba_pg_sz */
41504152
roce_set_field(eqc->byte_8,
41514153
HNS_ROCE_EQC_BA_PG_SZ_M,
4152-
HNS_ROCE_EQC_BA_PG_SZ_S, eq->eqe_ba_pg_sz);
4154+
HNS_ROCE_EQC_BA_PG_SZ_S,
4155+
eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
41534156

41544157
/* set eqe_buf_pg_sz */
41554158
roce_set_field(eqc->byte_8,
41564159
HNS_ROCE_EQC_BUF_PG_SZ_M,
4157-
HNS_ROCE_EQC_BUF_PG_SZ_S, eq->eqe_buf_pg_sz);
4160+
HNS_ROCE_EQC_BUF_PG_SZ_S,
4161+
eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
41584162

41594163
/* set eq_producer_idx */
41604164
roce_set_field(eqc->byte_8,

‎drivers/infiniband/hw/hns/hns_roce_mr.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1007,12 +1007,6 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
10071007
}
10081008

10091009
n = ib_umem_page_count(mr->umem);
1010-
if (mr->umem->page_shift != HNS_ROCE_HEM_PAGE_SHIFT) {
1011-
dev_err(dev, "Just support 4K page size but is 0x%lx now!\n",
1012-
BIT(mr->umem->page_shift));
1013-
ret = -EINVAL;
1014-
goto err_umem;
1015-
}
10161010

10171011
if (!hr_dev->caps.pbl_hop_num) {
10181012
if (n > HNS_ROCE_MAX_MTPT_PBL_NUM) {

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