ASoC: Intel: Skylake: Reset the controller in probe

gune42 · broonie · commit 60767abcea3d · 2017-08-01T13:33:58.000+01:00
Controller can be in reset state by default. Capability structure
traversal requires the controller to be out of reset else it
results in broken capability parsing. Hence make sure that controller is
out of reset before parsing capabilities by doing a full reset.

Signed-off-by: Guneshwor Singh &lt;guneshwor.o.singh@intel.com&gt;
Acked-By: Vinod Koul &lt;vinod.koul@intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
@@ -702,6 +702,8 @@ static int skl_first_init(struct hdac_ext_bus *ebus)
 		return -ENXIO;
 	}
 
+	skl_init_chip(bus, true);
+
 	snd_hdac_bus_parse_capabilities(bus);
 
 	if (skl_acquire_irq(ebus, 0) < 0)

Original file line number	Diff line number	Diff line change
`@@ -702,6 +702,8 @@ static int skl_first_init(struct hdac_ext_bus *ebus)`
`702`	`702`	`return -ENXIO;`
`703`	`703`	`}`
`704`	`704`
	`705`	`+ skl_init_chip(bus, true);`
	`706`	`+`
`705`	`707`	`snd_hdac_bus_parse_capabilities(bus);`
`706`	`708`
`707`	`709`	`if (skl_acquire_irq(ebus, 0) < 0)`