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rafaeljwrafaeljw
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Merge branches 'acpica-fixes', 'acpi-video' and 'acpi-processor'
* acpica-fixes: ACPICA / Hardware: Fix old register check in acpi_hw_get_access_bit_width() * acpi-video: ACPI / Thermal / video: fix max_level incorrect value * acpi-processor: ACPI / processor: Avoid reserving IO regions too early
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‎.gitignore

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@@ -62,7 +62,7 @@ Module.symvers
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/tar-install/
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#
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# git files that we don't want to ignore even it they are dot-files
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# git files that we don't want to ignore even if they are dot-files
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#
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!.gitignore
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!.mailmap

‎.mailmap

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@@ -69,6 +69,7 @@ Jean Tourrilhes <[email protected]>
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Jeff Garzik <[email protected]>
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Jens Axboe <[email protected]>
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Jens Osterkamp <[email protected]>
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John Paul Adrian Glaubitz <[email protected]>
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John Stultz <[email protected]>
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<[email protected]> <[email protected]>
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<[email protected]> <[email protected]>

‎CREDITS

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@@ -768,6 +768,7 @@ D: Z85230 driver
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D: Former security contact point (please use [email protected])
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D: ex 2.2 maintainer
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D: 2.1.x modular sound
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D: Assigned major/minor numbers maintainer at lanana.org
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S: c/o Red Hat UK Ltd
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S: Alexandra House
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S: Alexandra Terrace

‎Documentation/ABI/obsolete/sysfs-driver-hid-roccat-savu

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@@ -3,9 +3,10 @@ Date: Mai 2012
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Contact: Stefan Achatz <[email protected]>
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Description: The mouse can store 5 profiles which can be switched by the
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press of a button. A profile is split into general settings and
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button settings. buttons holds informations about button layout.
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When written, this file lets one write the respective profile
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buttons to the mouse. The data has to be 47 bytes long.
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button settings. The buttons variable holds information about
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button layout. When written, this file lets one write the
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respective profile buttons to the mouse. The data has to be
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47 bytes long.
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The mouse will reject invalid data.
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Which profile to write is determined by the profile number
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contained in the data.
@@ -26,8 +27,8 @@ Date: Mai 2012
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Contact: Stefan Achatz <[email protected]>
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Description: The mouse can store 5 profiles which can be switched by the
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press of a button. A profile is split into general settings and
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button settings. profile holds informations like resolution, sensitivity
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and light effects.
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button settings. A profile holds information like resolution,
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sensitivity and light effects.
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When written, this file lets one write the respective profile
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settings back to the mouse. The data has to be 43 bytes long.
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The mouse will reject invalid data.

‎Documentation/ABI/stable/sysfs-class-ubi

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@@ -107,6 +107,15 @@ Contact: Artem Bityutskiy <[email protected]>
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Description:
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Number of physical eraseblocks reserved for bad block handling.
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What: /sys/class/ubi/ubiX/ro_mode
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Date: April 2016
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KernelVersion: 4.7
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Contact: [email protected]
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Description:
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Contains ASCII "1\n" if the read-only flag is set on this
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device, and "0\n" if it is cleared. UBI devices mark themselves
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as read-only when they detect an unrecoverable error.
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What: /sys/class/ubi/ubiX/total_eraseblocks
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Date: July 2006
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KernelVersion: 2.6.22

‎Documentation/ABI/testing/sysfs-block-zram

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@@ -166,3 +166,12 @@ Description:
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The mm_stat file is read-only and represents device's mm
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statistics (orig_data_size, compr_data_size, etc.) in a format
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similar to block layer statistics file format.
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What: /sys/block/zram<id>/debug_stat
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Date: July 2016
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Contact: Sergey Senozhatsky <[email protected]>
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Description:
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The debug_stat file is read-only and represents various
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device's debugging info useful for kernel developers. Its
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format is not documented intentionally and may change
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anytime without any notice.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10

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@@ -6,13 +6,6 @@ Description: (RW) Add/remove a sink from a trace path. There can be multiple
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source for a single sink.
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ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
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What: /sys/bus/coresight/devices/<memory_map>.etb/status
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) List various control and status registers. The specific
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layout and content is driver specific.
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What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
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Date: November 2014
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KernelVersion: 3.19
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following the trigger event. The number of 32-bit words written
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into the Trace RAM following the trigger event is equal to the
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value stored in this register+1 (from ARM ETB-TRM).
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Defines the depth, in words, of the trace RAM in powers of
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2. The value is read directly from HW register RDP, 0x004.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the ETB status register. The value
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is read directly from HW register STS, 0x00C.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the ETB RAM Read Pointer register
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that is used to read entries from the Trace RAM over the APB
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interface. The value is read directly from HW register RRP,
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0x014.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the ETB RAM Write Pointer register
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that is used to sets the write pointer to write entries from
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the CoreSight bus into the Trace RAM. The value is read directly
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from HW register RWP, 0x018.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Similar to "trigger_cntr" above except that this value is
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read directly from HW register TRG, 0x01C.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the ETB Control register. The value
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is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the ETB Formatter and Flush Status
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register. The value is read directly from HW register FFSR,
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0x300.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the ETB Formatter and Flush Control
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register. The value is read directly from HW register FFCR,
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0x304.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

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Description: (R) Print the content of the Peripheral ID3 Register
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(0xFEC). The value is taken directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
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Date: February 2016
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KernelVersion: 4.07
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Print the content of the trace configuration register
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(0x010) as currently set by SW.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
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Date: February 2016
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KernelVersion: 4.07
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Print the content of the trace ID register (0x040).
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What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
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Date: April 2015
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KernelVersion: 4.01

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-stm

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What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (RW) Enable/disable tracing on this specific trace macrocell.
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Enabling the trace macrocell implies it has been configured
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properly and a sink has been identified for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (RW) Provides access to the HW event enable register, used in
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conjunction with HW event bank select register.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (RW) Gives access to the HW event block select register
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(STMHEBSR) in order to configure up to 256 channels. Used in
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conjunction with "hwevent_enable" register as described above.
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What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (RW) Provides access to the stimulus port enable register
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(STMSPER). Used in conjunction with "port_select" described
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below.
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What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (RW) Used to determine which bank of stimulus port bit in
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register STMSPER (see above) apply to.
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What: /sys/bus/coresight/devices/<memory_map>.stm/status
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) List various control and status registers. The specific
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layout and content is driver specific.
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What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (RW) Holds the trace ID that will appear in the trace stream
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coming from this trace entity.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc

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formatter after a defined number of words have been stored
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following the trigger event. Additional interface for this
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driver are expected to be added as it matures.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Defines the size, in 32-bit words, of the local RAM buffer.
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The value is read directly from HW register RSZ, 0x004.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC status register. The value
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is read directly from HW register STS, 0x00C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC RAM Read Pointer register
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that is used to read entries from the Trace RAM over the APB
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interface. The value is read directly from HW register RRP,
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0x014.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC RAM Write Pointer register
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that is used to sets the write pointer to write entries from
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the CoreSight bus into the Trace RAM. The value is read directly
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from HW register RWP, 0x018.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Similar to "trigger_cntr" above except that this value is
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read directly from HW register TRG, 0x01C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC Control register. The value
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is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC Formatter and Flush Status
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register. The value is read directly from HW register FFSR,
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0x300.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC Formatter and Flush Control
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register. The value is read directly from HW register FFCR,
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0x304.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Shows the value held by the TMC Mode register, which
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indicate the mode the device has been configured to enact. The
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The value is read directly from the MODE register, 0x028.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <[email protected]>
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Description: (R) Indicates the capabilities of the Coresight TMC.
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The value is read directly from the DEVID register, 0xFC8,

‎Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7

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@@ -4,7 +4,7 @@ Contact: Linux on PowerPC Developer List <[email protected]>
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Description:
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Provides access to the binary "24x7 catalog" provided by the
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hypervisor on POWER7 and 8 systems. This catalog lists events
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avaliable from the powerpc "hv_24x7" pmu. Its format is
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available from the powerpc "hv_24x7" pmu. Its format is
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documented here:
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https://raw.githubusercontent.com/jmesmon/catalog-24x7/master/hv-24x7-catalog.h
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