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abdoulaye berthealexdeucher
abdoulaye berthe
authored and
alexdeucher
committed
drm/amd/display: disable lttpr for invalid lttpr caps.
1-Read lttpr caps in 5-bytes 2-Parse caps 3-Validate caps and set lttpr_mode 4-Use hw default timeout when lttpr is disabled. Signed-off-by: abdoulaye berthe <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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3 files changed

+49
-58
lines changed

3 files changed

+49
-58
lines changed

‎drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 46 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1172,15 +1172,15 @@ static void configure_lttpr_mode(struct dc_link *link)
11721172
uint8_t repeater_cnt;
11731173
uint32_t aux_interval_address;
11741174
uint8_t repeater_id;
1175-
enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
1175+
uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
11761176

11771177
core_link_write_dpcd(link,
11781178
DP_PHY_REPEATER_MODE,
11791179
(uint8_t *)&repeater_mode,
11801180
sizeof(repeater_mode));
11811181

11821182
if (!link->is_lttpr_mode_transparent) {
1183-
repeater_mode = phy_repeater_mode_non_transparent;
1183+
repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
11841184
core_link_write_dpcd(link,
11851185
DP_PHY_REPEATER_MODE,
11861186
(uint8_t *)&repeater_mode,
@@ -2964,7 +2964,11 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
29642964

29652965
static bool retrieve_link_cap(struct dc_link *link)
29662966
{
2967-
uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
2967+
/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
2968+
* which means size 16 will be good for both of those DPCD register block reads
2969+
*/
2970+
uint8_t dpcd_data[16];
2971+
uint8_t lttpr_dpcd_data[6];
29682972

29692973
/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
29702974
*/
@@ -2977,7 +2981,6 @@ static bool retrieve_link_cap(struct dc_link *link)
29772981
union dp_downstream_port_present ds_port = { 0 };
29782982
enum dc_status status = DC_ERROR_UNEXPECTED;
29792983
uint32_t read_dpcd_retry_cnt = 3;
2980-
uint32_t prev_timeout_val;
29812984
int i;
29822985
struct dp_sink_hw_fw_revision dp_hw_fw_revision;
29832986

@@ -2988,12 +2991,12 @@ static bool retrieve_link_cap(struct dc_link *link)
29882991
link->is_lttpr_mode_transparent = true;
29892992

29902993
if (ext_timeout_support) {
2991-
prev_timeout_val =
2992-
dc_link_aux_configure_timeout(link->ddc,
2993-
LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
2994+
dc_link_aux_configure_timeout(link->ddc,
2995+
LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
29942996
}
29952997

29962998
memset(dpcd_data, '\0', sizeof(dpcd_data));
2999+
memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
29973000
memset(&down_strm_port_count,
29983001
'\0', sizeof(union down_stream_port_count));
29993002
memset(&edp_config_cap, '\0',
@@ -3026,47 +3029,46 @@ static bool retrieve_link_cap(struct dc_link *link)
30263029
}
30273030

30283031
if (ext_timeout_support) {
3032+
30293033
status = core_link_read_dpcd(
30303034
link,
3031-
DP_PHY_REPEATER_CNT,
3032-
&link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
3033-
sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
3034-
3035-
if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0) {
3036-
3035+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3036+
lttpr_dpcd_data,
3037+
sizeof(lttpr_dpcd_data));
3038+
3039+
link->dpcd_caps.lttpr_caps.revision.raw =
3040+
lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3041+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3042+
3043+
link->dpcd_caps.lttpr_caps.max_link_rate =
3044+
lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3045+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3046+
3047+
link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3048+
lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3049+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3050+
3051+
link->dpcd_caps.lttpr_caps.max_lane_count =
3052+
lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3053+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3054+
3055+
link->dpcd_caps.lttpr_caps.mode =
3056+
lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3057+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3058+
3059+
link->dpcd_caps.lttpr_caps.max_ext_timeout =
3060+
lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3061+
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3062+
3063+
if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3064+
link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3065+
link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3066+
link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {
30373067
link->is_lttpr_mode_transparent = false;
3038-
3039-
status = core_link_read_dpcd(
3040-
link,
3041-
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3042-
(uint8_t *)&link->dpcd_caps.lttpr_caps.revision,
3043-
sizeof(link->dpcd_caps.lttpr_caps.revision));
3044-
3045-
status = core_link_read_dpcd(
3046-
link,
3047-
DP_MAX_LINK_RATE_PHY_REPEATER,
3048-
&link->dpcd_caps.lttpr_caps.max_link_rate,
3049-
sizeof(link->dpcd_caps.lttpr_caps.max_link_rate));
3050-
3051-
status = core_link_read_dpcd(
3052-
link,
3053-
DP_PHY_REPEATER_MODE,
3054-
(uint8_t *)&link->dpcd_caps.lttpr_caps.mode,
3055-
sizeof(link->dpcd_caps.lttpr_caps.mode));
3056-
3057-
status = core_link_read_dpcd(
3058-
link,
3059-
DP_MAX_LANE_COUNT_PHY_REPEATER,
3060-
&link->dpcd_caps.lttpr_caps.max_lane_count,
3061-
sizeof(link->dpcd_caps.lttpr_caps.max_lane_count));
3062-
3063-
status = core_link_read_dpcd(
3064-
link,
3065-
DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
3066-
&link->dpcd_caps.lttpr_caps.max_ext_timeout,
3067-
sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
30683068
} else {
3069-
dc_link_aux_configure_timeout(link->ddc, prev_timeout_val);
3069+
/*No lttpr reset timeout to its default value*/
3070+
link->is_lttpr_mode_transparent = true;
3071+
dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
30703072
}
30713073
}
30723074

‎drivers/gpu/drm/amd/display/dc/dc_types.h

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -420,20 +420,9 @@ enum link_training_offset {
420420
LTTPR_PHY_REPEATER8 = 8
421421
};
422422

423-
enum lttpr_mode {
424-
phy_repeater_mode_transparent = 0x55,
425-
phy_repeater_mode_non_transparent = 0xAA
426-
};
427-
428-
enum lttpr_rev {
429-
lttpr_rev_unknown = 0x0,
430-
lttpr_rev_14 = 0x14,
431-
lttpr_rev_max = 0x20
432-
};
433-
434423
struct dc_lttpr_caps {
435-
enum lttpr_rev revision;
436-
enum lttpr_mode mode;
424+
union dpcd_rev revision;
425+
uint8_t mode;
437426
uint8_t max_lane_count;
438427
uint8_t max_link_rate;
439428
uint8_t phy_repeater_cnt;

‎drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
#define LINK_TRAINING_ATTEMPTS 4
3030
#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
3131
#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
32-
#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
32+
#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
3333

3434
struct dc_link;
3535
struct dc_stream_state;

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