igc: Set QBVCYCLET_S to 0 for TSN Basic Scheduling

zulkifl3 · anguy11 · commit 62f5bbfb2afd · 2021-07-20T16:11:36.000-07:00
According to datasheet section 8.12.19, when there's no TSN offloading
Shadow_QbvCycle bit[29:0] must be set to zero for basic scheduling.

Signed-off-by: Muhammad Husaini Zulkifli &lt;muhammad.husaini.zulkifli@intel.com&gt;
Tested-by: Dvora Fuxbrumer &lt;dvorax.fuxbrumer@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c
@@ -52,7 +52,7 @@ static int igc_tsn_disable_offload(struct igc_adapter *adapter)
 		wr32(IGC_ENDQT(i), NSEC_PER_SEC);
 	}
 
-	wr32(IGC_QBVCYCLET_S, NSEC_PER_SEC);
+	wr32(IGC_QBVCYCLET_S, 0);
 	wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
 
 	adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;

Original file line number	Diff line number	Diff line change
`@@ -52,7 +52,7 @@ static int igc_tsn_disable_offload(struct igc_adapter *adapter)`
`52`	`52`	`wr32(IGC_ENDQT(i), NSEC_PER_SEC);`
`53`	`53`	`}`
`54`	`54`
`55`		`- wr32(IGC_QBVCYCLET_S, NSEC_PER_SEC);`
	`55`	`+ wr32(IGC_QBVCYCLET_S, 0);`
`56`	`56`	`wr32(IGC_QBVCYCLET, NSEC_PER_SEC);`
`57`	`57`
`58`	`58`	`adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;`