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net: phy: microchip_t1: add lan87xx_phy_init to initialize the lan87xx phy.
lan87xx_phy_init() initializes the lan87xx phy hardware including its TC10 Wake-up and Sleep features. Fixes: 3e50d2d ("Add driver for Microchip LAN87XX T1 PHYs") Signed-off-by: Yuiko Oshino <[email protected]> v0->v1: - Add more details in the commit message and source comments. - Update to the latest initialization sequences. - Add access_ereg_modify_changed(). - Fix access_ereg() to access SMI bank correctly. Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/phy/microchip_t1.c

Lines changed: 171 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,21 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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/* External Register Control Register */
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#define LAN87XX_EXT_REG_CTL (0x14)
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#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
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#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
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/* External Register Read Data Register */
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#define LAN87XX_EXT_REG_RD_DATA (0x15)
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/* External Register Write Data Register */
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#define LAN87XX_EXT_REG_WR_DATA (0x16)
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/* Interrupt Source Register */
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#define LAN87XX_INTERRUPT_SOURCE (0x18)
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@@ -14,9 +26,160 @@
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#define LAN87XX_MASK_LINK_UP (0x0004)
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#define LAN87XX_MASK_LINK_DOWN (0x0002)
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/* phyaccess nested types */
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#define PHYACC_ATTR_MODE_READ 0
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#define PHYACC_ATTR_MODE_WRITE 1
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#define PHYACC_ATTR_MODE_MODIFY 2
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#define PHYACC_ATTR_BANK_SMI 0
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#define PHYACC_ATTR_BANK_MISC 1
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#define PHYACC_ATTR_BANK_PCS 2
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#define PHYACC_ATTR_BANK_AFE 3
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#define PHYACC_ATTR_BANK_MAX 7
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#define DRIVER_AUTHOR "Nisar Sayed <[email protected]>"
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#define DRIVER_DESC "Microchip LAN87XX T1 PHY driver"
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struct access_ereg_val {
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u8 mode;
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u8 bank;
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u8 offset;
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u16 val;
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u16 mask;
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};
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static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
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u8 offset, u16 val)
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{
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u16 ereg = 0;
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int rc = 0;
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if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)
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return -EINVAL;
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if (bank == PHYACC_ATTR_BANK_SMI) {
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if (mode == PHYACC_ATTR_MODE_WRITE)
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rc = phy_write(phydev, offset, val);
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else
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rc = phy_read(phydev, offset);
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return rc;
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}
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if (mode == PHYACC_ATTR_MODE_WRITE) {
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ereg = LAN87XX_EXT_REG_CTL_WR_CTL;
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rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);
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if (rc < 0)
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return rc;
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} else {
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ereg = LAN87XX_EXT_REG_CTL_RD_CTL;
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}
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ereg |= (bank << 8) | offset;
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rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
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if (rc < 0)
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return rc;
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if (mode == PHYACC_ATTR_MODE_READ)
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rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA);
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return rc;
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}
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static int access_ereg_modify_changed(struct phy_device *phydev,
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u8 bank, u8 offset, u16 val, u16 mask)
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{
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int new = 0, rc = 0;
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if (bank > PHYACC_ATTR_BANK_MAX)
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return -EINVAL;
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rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);
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if (rc < 0)
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return rc;
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new = val | (rc & (mask ^ 0xFFFF));
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rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
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return rc;
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}
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static int lan87xx_phy_init(struct phy_device *phydev)
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{
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static const struct access_ereg_val init[] = {
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/* TX Amplitude = 5 */
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{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_AFE, 0x0B,
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0x000A, 0x001E},
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/* Clear SMI interrupts */
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{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 0x18,
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0, 0},
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/* Clear MISC interrupts */
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{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 0x08,
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0, 0},
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/* Turn on TC10 Ring Oscillator (ROSC) */
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{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_MISC, 0x20,
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0x0020, 0x0020},
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/* WUR Detect Length to 1.2uS, LPC Detect Length to 1.09uS */
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{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_PCS, 0x20,
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0x283C, 0},
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/* Wake_In Debounce Length to 39uS, Wake_Out Length to 79uS */
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{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x21,
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0x274F, 0},
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/* Enable Auto Wake Forward to Wake_Out, ROSC on, Sleep,
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* and Wake_In to wake PHY
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*/
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{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20,
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0x80A7, 0},
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/* Enable WUP Auto Fwd, Enable Wake on MDI, Wakeup Debouncer
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* to 128 uS
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*/
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{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x24,
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0xF110, 0},
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/* Enable HW Init */
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{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_SMI, 0x1A,
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0x0100, 0x0100},
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};
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int rc, i;
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/* Start manual initialization procedures in Managed Mode */
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rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
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0x1a, 0x0000, 0x0100);
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if (rc < 0)
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return rc;
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/* Soft Reset the SMI block */
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rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
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0x00, 0x8000, 0x8000);
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if (rc < 0)
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return rc;
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/* Check to see if the self-clearing bit is cleared */
157+
usleep_range(1000, 2000);
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rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
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PHYACC_ATTR_BANK_SMI, 0x00, 0);
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if (rc < 0)
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return rc;
162+
if ((rc & 0x8000) != 0)
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return -ETIMEDOUT;
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/* PHY Initialization */
166+
for (i = 0; i < ARRAY_SIZE(init); i++) {
167+
if (init[i].mode == PHYACC_ATTR_MODE_MODIFY) {
168+
rc = access_ereg_modify_changed(phydev, init[i].bank,
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init[i].offset,
170+
init[i].val,
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init[i].mask);
172+
} else {
173+
rc = access_ereg(phydev, init[i].mode, init[i].bank,
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init[i].offset, init[i].val);
175+
}
176+
if (rc < 0)
177+
return rc;
178+
}
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180+
return 0;
181+
}
182+
20183
static int lan87xx_phy_config_intr(struct phy_device *phydev)
21184
{
22185
int rc, val = 0;
@@ -40,6 +203,13 @@ static int lan87xx_phy_ack_interrupt(struct phy_device *phydev)
40203
return rc < 0 ? rc : 0;
41204
}
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206+
static int lan87xx_config_init(struct phy_device *phydev)
207+
{
208+
int rc = lan87xx_phy_init(phydev);
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210+
return rc < 0 ? rc : 0;
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}
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43213
static struct phy_driver microchip_t1_phy_driver[] = {
44214
{
45215
.phy_id = 0x0007c150,
@@ -48,6 +218,7 @@ static struct phy_driver microchip_t1_phy_driver[] = {
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.features = PHY_BASIC_T1_FEATURES,
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.config_init = lan87xx_config_init,
51222
.config_aneg = genphy_config_aneg,
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.ack_interrupt = lan87xx_phy_ack_interrupt,

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