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Yoshihiro Shimodadavem330
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net: sh_eth: Add support SH7724
Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Nobuhiro Iwamatsu <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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-6
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3 files changed

+111
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lines changed

drivers/net/Kconfig

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -516,15 +516,16 @@ config STNIC
516516
config SH_ETH
517517
tristate "Renesas SuperH Ethernet support"
518518
depends on SUPERH && \
519-
(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763 || \
520-
CPU_SUBTYPE_SH7619)
519+
(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || \
520+
CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7619 || \
521+
CPU_SUBTYPE_SH7724)
521522
select CRC32
522523
select MII
523524
select MDIO_BITBANG
524525
select PHYLIB
525526
help
526527
Renesas SuperH Ethernet device driver.
527-
This driver support SH7710, SH7712, SH7763 and SH7619.
528+
This driver support SH7710, SH7712, SH7763, SH7619, and SH7724.
528529

529530
config SUNLANCE
530531
tristate "Sun LANCE support"

drivers/net/sh_eth.c

Lines changed: 51 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,57 @@
3434
#include "sh_eth.h"
3535

3636
/* There is CPU dependent code */
37-
#if defined(CONFIG_CPU_SUBTYPE_SH7763)
37+
#if defined(CONFIG_CPU_SUBTYPE_SH7724)
38+
#define SH_ETH_RESET_DEFAULT 1
39+
static void sh_eth_set_duplex(struct net_device *ndev)
40+
{
41+
struct sh_eth_private *mdp = netdev_priv(ndev);
42+
u32 ioaddr = ndev->base_addr;
43+
44+
if (mdp->duplex) /* Full */
45+
ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
46+
else /* Half */
47+
ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
48+
}
49+
50+
static void sh_eth_set_rate(struct net_device *ndev)
51+
{
52+
struct sh_eth_private *mdp = netdev_priv(ndev);
53+
u32 ioaddr = ndev->base_addr;
54+
55+
switch (mdp->speed) {
56+
case 10: /* 10BASE */
57+
ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
58+
break;
59+
case 100:/* 100BASE */
60+
ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
61+
break;
62+
default:
63+
break;
64+
}
65+
}
66+
67+
/* SH7724 */
68+
static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
69+
.set_duplex = sh_eth_set_duplex,
70+
.set_rate = sh_eth_set_rate,
71+
72+
.ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
73+
.ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
74+
.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
75+
76+
.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
77+
.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
78+
EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
79+
.tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
80+
81+
.apr = 1,
82+
.mpr = 1,
83+
.tpauser = 1,
84+
.hw_swap = 1,
85+
};
86+
87+
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
3888
#define SH_ETH_HAS_TSU 1
3989
static void sh_eth_chip_reset(struct net_device *ndev)
4090
{

drivers/net/sh_eth.h

Lines changed: 56 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@
4040
#define PKT_BUF_SZ 1538
4141

4242
#if defined(CONFIG_CPU_SUBTYPE_SH7763)
43+
/* This CPU register maps is very difference by other SH4 CPU */
44+
4345
/* Chip Base Address */
4446
# define SH_TSU_ADDR 0xFEE01800
4547
# define ARSTR SH_TSU_ADDR
@@ -141,7 +143,59 @@
141143
# define FWNLCR1 0xB0
142144
# define FWALCR1 0x40
143145

144-
#else /* #elif defined(CONFIG_CPU_SUBTYPE_SH7763) */
146+
#elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */
147+
/* EtherC */
148+
#define ECMR 0x100
149+
#define RFLR 0x108
150+
#define ECSR 0x110
151+
#define ECSIPR 0x118
152+
#define PIR 0x120
153+
#define PSR 0x128
154+
#define RDMLR 0x140
155+
#define IPGR 0x150
156+
#define APR 0x154
157+
#define MPR 0x158
158+
#define TPAUSER 0x164
159+
#define RFCF 0x160
160+
#define TPAUSECR 0x168
161+
#define BCFRR 0x16c
162+
#define MAHR 0x1c0
163+
#define MALR 0x1c8
164+
#define TROCR 0x1d0
165+
#define CDCR 0x1d4
166+
#define LCCR 0x1d8
167+
#define CNDCR 0x1dc
168+
#define CEFCR 0x1e4
169+
#define FRECR 0x1e8
170+
#define TSFRCR 0x1ec
171+
#define TLFRCR 0x1f0
172+
#define RFCR 0x1f4
173+
#define MAFCR 0x1f8
174+
#define RTRATE 0x1fc
175+
176+
/* E-DMAC */
177+
#define EDMR 0x000
178+
#define EDTRR 0x008
179+
#define EDRRR 0x010
180+
#define TDLAR 0x018
181+
#define RDLAR 0x020
182+
#define EESR 0x028
183+
#define EESIPR 0x030
184+
#define TRSCER 0x038
185+
#define RMFCR 0x040
186+
#define TFTR 0x048
187+
#define FDR 0x050
188+
#define RMCR 0x058
189+
#define TFUCR 0x064
190+
#define RFOCR 0x068
191+
#define FCFTR 0x070
192+
#define RPADIR 0x078
193+
#define TRIMD 0x07c
194+
#define RBWAR 0x0c8
195+
#define RDFAR 0x0cc
196+
#define TBRAR 0x0d4
197+
#define TDFAR 0x0d8
198+
#else /* #elif defined(CONFIG_CPU_SH4) */
145199
/* This section is SH3 or SH2 */
146200
#ifndef CONFIG_CPU_SUBTYPE_SH7619
147201
/* Chip base address */
@@ -426,7 +480,7 @@ enum FELIC_MODE_BIT {
426480
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
427481
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
428482
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
429-
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
483+
ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
430484
ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
431485
};
432486

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