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superna9999Boris Brezillon
superna9999
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Boris Brezillon
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mtd: nand: Add OX820 NAND Support
Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller. This is a simple memory mapped NAND controller with single chip select and software ECC. Acked-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
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‎Documentation/devicetree/bindings/mtd/oxnas-nand.txt

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* Oxford Semiconductor OXNAS NAND Controller
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Please refer to nand.txt for generic information regarding MTD NAND bindings.
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Required properties:
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- compatible: "oxsemi,ox820-nand"
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- reg: Base address and length for NAND mapped memory.
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Optional Properties:
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- clocks: phandle to the NAND gate clock if needed.
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- resets: phandle to the NAND reset control if needed.
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Example:
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nandc: nand-controller@41000000 {
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compatible = "oxsemi,ox820-nand";
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reg = <0x41000000 0x100000>;
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clocks = <&stdclk CLK_820_NAND>;
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resets = <&reset RESET_NAND>;
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "hamming";
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partition@0 {
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label = "boot";
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reg = <0x00000000 0x00e00000>;
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read-only;
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};
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partition@e00000 {
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label = "ubi";
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reg = <0x00e00000 0x07200000>;
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};
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};
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};

‎drivers/mtd/nand/Kconfig

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@@ -426,6 +426,11 @@ config MTD_NAND_ORION
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No board specific support is done by this driver, each board
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must advertise a platform_device for the driver to attach.
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config MTD_NAND_OXNAS
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tristate "NAND Flash support for Oxford Semiconductor SoC"
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help
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This enables the NAND flash controller on Oxford Semiconductor SoCs.
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config MTD_NAND_FSL_ELBC
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tristate "NAND support for Freescale eLBC controllers"
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depends on FSL_SOC

‎drivers/mtd/nand/Makefile

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@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
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obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
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obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
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obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
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obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o

‎drivers/mtd/nand/oxnas_nand.c

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/*
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* Oxford Semiconductor OXNAS NAND driver
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* Copyright (C) 2016 Neil Armstrong <[email protected]>
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* Heavily based on plat_nand.c :
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* Author: Vitaly Wool <[email protected]>
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* Copyright (C) 2013 Ma Haijun <[email protected]>
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* Copyright (C) 2012 John Crispin <[email protected]>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/of.h>
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/* Nand commands */
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#define OXNAS_NAND_CMD_ALE BIT(18)
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#define OXNAS_NAND_CMD_CLE BIT(19)
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#define OXNAS_NAND_MAX_CHIPS 1
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struct oxnas_nand_ctrl {
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struct nand_hw_control base;
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void __iomem *io_base;
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struct clk *clk;
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struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
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};
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static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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return readb(oxnas->io_base);
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}
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static void oxnas_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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ioread8_rep(oxnas->io_base, buf, len);
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}
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static void oxnas_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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iowrite8_rep(oxnas->io_base, buf, len);
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}
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/* Single CS command control */
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static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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if (ctrl & NAND_CLE)
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writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
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else if (ctrl & NAND_ALE)
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writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
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}
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/*
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* Probe for the NAND device.
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*/
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static int oxnas_nand_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device_node *nand_np;
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struct oxnas_nand_ctrl *oxnas;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct resource *res;
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int nchips = 0;
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int count = 0;
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int err = 0;
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/* Allocate memory for the device structure (and zero it) */
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oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
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GFP_KERNEL);
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if (!oxnas)
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return -ENOMEM;
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nand_hw_control_init(&oxnas->base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(oxnas->io_base))
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return PTR_ERR(oxnas->io_base);
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oxnas->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(oxnas->clk))
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oxnas->clk = NULL;
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/* Only a single chip node is supported */
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count = of_get_child_count(np);
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if (count > 1)
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return -EINVAL;
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clk_prepare_enable(oxnas->clk);
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device_reset_optional(&pdev->dev);
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for_each_child_of_node(np, nand_np) {
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chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
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GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->controller = &oxnas->base;
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nand_set_flash_node(chip, nand_np);
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nand_set_controller_data(chip, oxnas);
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mtd = nand_to_mtd(chip);
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mtd->dev.parent = &pdev->dev;
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mtd->priv = chip;
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chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
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chip->read_buf = oxnas_nand_read_buf;
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chip->read_byte = oxnas_nand_read_byte;
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chip->write_buf = oxnas_nand_write_buf;
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chip->chip_delay = 30;
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/* Scan to find existence of the device */
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err = nand_scan(mtd, 1);
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if (err)
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return err;
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err = mtd_device_register(mtd, NULL, 0);
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if (err) {
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nand_release(mtd);
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return err;
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}
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oxnas->chips[nchips] = chip;
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++nchips;
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}
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/* Exit if no chips found */
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if (!nchips)
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return -ENODEV;
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platform_set_drvdata(pdev, oxnas);
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return 0;
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}
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static int oxnas_nand_remove(struct platform_device *pdev)
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{
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struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
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if (oxnas->chips[0])
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nand_release(nand_to_mtd(oxnas->chips[0]));
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clk_disable_unprepare(oxnas->clk);
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return 0;
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}
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static const struct of_device_id oxnas_nand_match[] = {
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{ .compatible = "oxsemi,ox820-nand" },
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{},
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};
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MODULE_DEVICE_TABLE(of, oxnas_nand_match);
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static struct platform_driver oxnas_nand_driver = {
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.probe = oxnas_nand_probe,
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.remove = oxnas_nand_remove,
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.driver = {
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.name = "oxnas_nand",
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.of_match_table = oxnas_nand_match,
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},
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};
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module_platform_driver(oxnas_nand_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Neil Armstrong <[email protected]>");
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MODULE_DESCRIPTION("Oxnas NAND driver");
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MODULE_ALIAS("platform:oxnas_nand");

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