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torvaldstorvalds
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Merge tag 'drm-fixes-2020-03-20' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Hope you are well hiding out above the garage. A few amdgpu changes but nothing too major. I've had a wisdom tooth out this week so haven't been to on top of things, but all seems good. core: - fix lease warning i915: - Track active elements during dequeue - Fix failure to handle all MCR ranges - Revert unnecessary workaround amdgpu: - Pageflip fix - VCN clockgating fixes - GPR debugfs fix for umr - GPU reset fix - eDP fix for MBP - DCN2.x fix dw-hdmi: - fix AVI frame colorimetry komeda: - fix compiler warning bochs: - downgrade a binding failure to a warning" * tag 'drm-fixes-2020-03-20' of git://anongit.freedesktop.org/drm/drm: drm/amd/display: Fix pageflip event race condition for DCN. drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check drm/amdgpu: fix typo for vcn2/jpeg2 idle check drm/amdgpu: fix typo for vcn1 idle check drm/lease: fix WARNING in idr_destroy drm/i915: Handle all MCR ranges Revert "drm/i915/tgl: Add extra hdc flush workaround" drm/i915/execlists: Track active elements during dequeue drm/bochs: downgrade pci_request_region failure from error to warning drm/amd/display: Add link_rate quirk for Apple 15" MBP 2017 drm/amdgpu: add fbdev suspend/resume on gpu reset drm/amd/amdgpu: Fix GPR read from debugfs (v2) drm/amd/display: fix typos for dcn20_funcs and dcn21_funcs struct drm/komeda: mark PM functions as __maybe_unused drm/bridge: dw-hdmi: fix AVI frame colorimetry
2 parents 6c90b86 + 5366b96 commit 69d3e5a

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17 files changed

+104
-83
lines changed

17 files changed

+104
-83
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -781,11 +781,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
781781
ssize_t result = 0;
782782
uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
783783

784-
if (size & 3 || *pos & 3)
784+
if (size > 4096 || size & 3 || *pos & 3)
785785
return -EINVAL;
786786

787787
/* decode offset */
788-
offset = *pos & GENMASK_ULL(11, 0);
788+
offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
789789
se = (*pos & GENMASK_ULL(19, 12)) >> 12;
790790
sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
791791
cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
@@ -823,7 +823,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
823823
while (size) {
824824
uint32_t value;
825825

826-
value = data[offset++];
826+
value = data[result >> 2];
827827
r = put_user(value, (uint32_t *)buf);
828828
if (r) {
829829
result = r;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3913,6 +3913,8 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
39133913
if (r)
39143914
goto out;
39153915

3916+
amdgpu_fbdev_set_suspend(tmp_adev, 0);
3917+
39163918
/* must succeed. */
39173919
amdgpu_ras_resume(tmp_adev);
39183920

@@ -4086,6 +4088,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
40864088
*/
40874089
amdgpu_unregister_gpu_instance(tmp_adev);
40884090

4091+
amdgpu_fbdev_set_suspend(adev, 1);
4092+
40894093
/* disable ras on ALL IPs */
40904094
if (!(in_ras_intr && !use_baco) &&
40914095
amdgpu_device_ip_need_full_reset(tmp_adev))

‎drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -693,7 +693,7 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
693693
bool enable = (state == AMD_CG_STATE_GATE);
694694

695695
if (enable) {
696-
if (jpeg_v2_0_is_idle(handle))
696+
if (!jpeg_v2_0_is_idle(handle))
697697
return -EBUSY;
698698
jpeg_v2_0_enable_clock_gating(adev);
699699
} else {

‎drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
477477
continue;
478478

479479
if (enable) {
480-
if (jpeg_v2_5_is_idle(handle))
480+
if (!jpeg_v2_5_is_idle(handle))
481481
return -EBUSY;
482482
jpeg_v2_5_enable_clock_gating(adev, i);
483483
} else {

‎drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1352,7 +1352,7 @@ static int vcn_v1_0_set_clockgating_state(void *handle,
13521352

13531353
if (enable) {
13541354
/* wait for STATUS to clear */
1355-
if (vcn_v1_0_is_idle(handle))
1355+
if (!vcn_v1_0_is_idle(handle))
13561356
return -EBUSY;
13571357
vcn_v1_0_enable_clock_gating(adev);
13581358
} else {

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1217,7 +1217,7 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
12171217

12181218
if (enable) {
12191219
/* wait for STATUS to clear */
1220-
if (vcn_v2_0_is_idle(handle))
1220+
if (!vcn_v2_0_is_idle(handle))
12211221
return -EBUSY;
12221222
vcn_v2_0_enable_clock_gating(adev);
12231223
} else {

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1672,7 +1672,7 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
16721672
return 0;
16731673

16741674
if (enable) {
1675-
if (vcn_v2_5_is_idle(handle))
1675+
if (!vcn_v2_5_is_idle(handle))
16761676
return -EBUSY;
16771677
vcn_v2_5_enable_clock_gating(adev);
16781678
} else {

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -522,8 +522,9 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params)
522522

523523
acrtc_state = to_dm_crtc_state(acrtc->base.state);
524524

525-
DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
526-
amdgpu_dm_vrr_active(acrtc_state));
525+
DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
526+
amdgpu_dm_vrr_active(acrtc_state),
527+
acrtc_state->active_planes);
527528

528529
amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
529530
drm_crtc_handle_vblank(&acrtc->base);
@@ -543,7 +544,18 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params)
543544
&acrtc_state->vrr_params.adjust);
544545
}
545546

546-
if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
547+
/*
548+
* If there aren't any active_planes then DCH HUBP may be clock-gated.
549+
* In that case, pageflip completion interrupts won't fire and pageflip
550+
* completion events won't get delivered. Prevent this by sending
551+
* pending pageflip events from here if a flip is still pending.
552+
*
553+
* If any planes are enabled, use dm_pflip_high_irq() instead, to
554+
* avoid race conditions between flip programming and completion,
555+
* which could cause too early flip completion events.
556+
*/
557+
if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
558+
acrtc_state->active_planes == 0) {
547559
if (acrtc->event) {
548560
drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
549561
acrtc->event = NULL;

‎drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3401,6 +3401,17 @@ static bool retrieve_link_cap(struct dc_link *link)
34013401
sink_id.ieee_device_id,
34023402
sizeof(sink_id.ieee_device_id));
34033403

3404+
/* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3405+
{
3406+
uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3407+
3408+
if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3409+
!memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3410+
sizeof(str_mbp_2017))) {
3411+
link->reported_link_cap.link_rate = 0x0c;
3412+
}
3413+
}
3414+
34043415
core_link_read_dpcd(
34053416
link,
34063417
DP_SINK_HW_REVISION_START,

‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,6 @@ static const struct hwseq_private_funcs dcn20_private_funcs = {
108108
.enable_power_gating_plane = dcn20_enable_power_gating_plane,
109109
.dpp_pg_control = dcn20_dpp_pg_control,
110110
.hubp_pg_control = dcn20_hubp_pg_control,
111-
.dsc_pg_control = NULL,
112111
.update_odm = dcn20_update_odm,
113112
.dsc_pg_control = dcn20_dsc_pg_control,
114113
.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,

‎drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,6 @@ static const struct hwseq_private_funcs dcn21_private_funcs = {
116116
.enable_power_gating_plane = dcn20_enable_power_gating_plane,
117117
.dpp_pg_control = dcn20_dpp_pg_control,
118118
.hubp_pg_control = dcn20_hubp_pg_control,
119-
.dsc_pg_control = NULL,
120119
.update_odm = dcn20_update_odm,
121120
.dsc_pg_control = dcn20_dsc_pg_control,
122121
.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,

‎drivers/gpu/drm/arm/display/komeda/komeda_drv.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,14 +146,14 @@ static const struct of_device_id komeda_of_match[] = {
146146

147147
MODULE_DEVICE_TABLE(of, komeda_of_match);
148148

149-
static int komeda_rt_pm_suspend(struct device *dev)
149+
static int __maybe_unused komeda_rt_pm_suspend(struct device *dev)
150150
{
151151
struct komeda_drv *mdrv = dev_get_drvdata(dev);
152152

153153
return komeda_dev_suspend(mdrv->mdev);
154154
}
155155

156-
static int komeda_rt_pm_resume(struct device *dev)
156+
static int __maybe_unused komeda_rt_pm_resume(struct device *dev)
157157
{
158158
struct komeda_drv *mdrv = dev_get_drvdata(dev);
159159

‎drivers/gpu/drm/bochs/bochs_hw.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -156,10 +156,8 @@ int bochs_hw_init(struct drm_device *dev)
156156
size = min(size, mem);
157157
}
158158

159-
if (pci_request_region(pdev, 0, "bochs-drm") != 0) {
160-
DRM_ERROR("Cannot request framebuffer\n");
161-
return -EBUSY;
162-
}
159+
if (pci_request_region(pdev, 0, "bochs-drm") != 0)
160+
DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
163161

164162
bochs->fb_map = ioremap(addr, size);
165163
if (bochs->fb_map == NULL) {

‎drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1624,28 +1624,34 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
16241624
frame.colorspace = HDMI_COLORSPACE_RGB;
16251625

16261626
/* Set up colorimetry */
1627-
switch (hdmi->hdmi_data.enc_out_encoding) {
1628-
case V4L2_YCBCR_ENC_601:
1629-
if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1630-
frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1631-
else
1627+
if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1628+
switch (hdmi->hdmi_data.enc_out_encoding) {
1629+
case V4L2_YCBCR_ENC_601:
1630+
if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1631+
frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1632+
else
1633+
frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1634+
frame.extended_colorimetry =
1635+
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1636+
break;
1637+
case V4L2_YCBCR_ENC_709:
1638+
if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1639+
frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1640+
else
1641+
frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1642+
frame.extended_colorimetry =
1643+
HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1644+
break;
1645+
default: /* Carries no data */
16321646
frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1647+
frame.extended_colorimetry =
1648+
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1649+
break;
1650+
}
1651+
} else {
1652+
frame.colorimetry = HDMI_COLORIMETRY_NONE;
16331653
frame.extended_colorimetry =
1634-
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1635-
break;
1636-
case V4L2_YCBCR_ENC_709:
1637-
if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1638-
frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1639-
else
1640-
frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1641-
frame.extended_colorimetry =
1642-
HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1643-
break;
1644-
default: /* Carries no data */
1645-
frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1646-
frame.extended_colorimetry =
1647-
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1648-
break;
1654+
HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
16491655
}
16501656

16511657
frame.scan_mode = HDMI_SCAN_MODE_NONE;

‎drivers/gpu/drm/drm_lease.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -542,10 +542,12 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
542542
}
543543

544544
DRM_DEBUG_LEASE("Creating lease\n");
545+
/* lessee will take the ownership of leases */
545546
lessee = drm_lease_create(lessor, &leases);
546547

547548
if (IS_ERR(lessee)) {
548549
ret = PTR_ERR(lessee);
550+
idr_destroy(&leases);
549551
goto out_leases;
550552
}
551553

@@ -580,7 +582,6 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
580582

581583
out_leases:
582584
put_unused_fd(fd);
583-
idr_destroy(&leases);
584585

585586
DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl failed: %d\n", ret);
586587
return ret;

‎drivers/gpu/drm/i915/gt/intel_lrc.c

Lines changed: 12 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1600,17 +1600,6 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve,
16001600
spin_unlock(&old->breadcrumbs.irq_lock);
16011601
}
16021602

1603-
static struct i915_request *
1604-
last_active(const struct intel_engine_execlists *execlists)
1605-
{
1606-
struct i915_request * const *last = READ_ONCE(execlists->active);
1607-
1608-
while (*last && i915_request_completed(*last))
1609-
last++;
1610-
1611-
return *last;
1612-
}
1613-
16141603
#define for_each_waiter(p__, rq__) \
16151604
list_for_each_entry_lockless(p__, \
16161605
&(rq__)->sched.waiters_list, \
@@ -1740,11 +1729,9 @@ static void record_preemption(struct intel_engine_execlists *execlists)
17401729
(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
17411730
}
17421731

1743-
static unsigned long active_preempt_timeout(struct intel_engine_cs *engine)
1732+
static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,
1733+
const struct i915_request *rq)
17441734
{
1745-
struct i915_request *rq;
1746-
1747-
rq = last_active(&engine->execlists);
17481735
if (!rq)
17491736
return 0;
17501737

@@ -1755,13 +1742,14 @@ static unsigned long active_preempt_timeout(struct intel_engine_cs *engine)
17551742
return READ_ONCE(engine->props.preempt_timeout_ms);
17561743
}
17571744

1758-
static void set_preempt_timeout(struct intel_engine_cs *engine)
1745+
static void set_preempt_timeout(struct intel_engine_cs *engine,
1746+
const struct i915_request *rq)
17591747
{
17601748
if (!intel_engine_has_preempt_reset(engine))
17611749
return;
17621750

17631751
set_timer_ms(&engine->execlists.preempt,
1764-
active_preempt_timeout(engine));
1752+
active_preempt_timeout(engine, rq));
17651753
}
17661754

17671755
static inline void clear_ports(struct i915_request **ports, int count)
@@ -1774,6 +1762,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
17741762
struct intel_engine_execlists * const execlists = &engine->execlists;
17751763
struct i915_request **port = execlists->pending;
17761764
struct i915_request ** const last_port = port + execlists->port_mask;
1765+
struct i915_request * const *active;
17771766
struct i915_request *last;
17781767
struct rb_node *rb;
17791768
bool submit = false;
@@ -1828,7 +1817,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
18281817
* i.e. we will retrigger preemption following the ack in case
18291818
* of trouble.
18301819
*/
1831-
last = last_active(execlists);
1820+
active = READ_ONCE(execlists->active);
1821+
while ((last = *active) && i915_request_completed(last))
1822+
active++;
1823+
18321824
if (last) {
18331825
if (need_preempt(engine, last, rb)) {
18341826
ENGINE_TRACE(engine,
@@ -2110,7 +2102,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
21102102
* Skip if we ended up with exactly the same set of requests,
21112103
* e.g. trying to timeslice a pair of ordered contexts
21122104
*/
2113-
if (!memcmp(execlists->active, execlists->pending,
2105+
if (!memcmp(active, execlists->pending,
21142106
(port - execlists->pending + 1) * sizeof(*port))) {
21152107
do
21162108
execlists_schedule_out(fetch_and_zero(port));
@@ -2121,7 +2113,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
21212113
clear_ports(port + 1, last_port - port);
21222114

21232115
execlists_submit_ports(engine);
2124-
set_preempt_timeout(engine);
2116+
set_preempt_timeout(engine, *active);
21252117
} else {
21262118
skip_submit:
21272119
ring_set_paused(engine, 0);
@@ -4008,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
40084000

40094001
*cs++ = preparser_disable(false);
40104002
intel_ring_advance(request, cs);
4011-
4012-
/*
4013-
* Wa_1604544889:tgl
4014-
*/
4015-
if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
4016-
flags = 0;
4017-
flags |= PIPE_CONTROL_CS_STALL;
4018-
flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
4019-
4020-
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4021-
flags |= PIPE_CONTROL_QW_WRITE;
4022-
4023-
cs = intel_ring_begin(request, 6);
4024-
if (IS_ERR(cs))
4025-
return PTR_ERR(cs);
4026-
4027-
cs = gen8_emit_pipe_control(cs, flags,
4028-
LRC_PPHWSP_SCRATCH_ADDR);
4029-
intel_ring_advance(request, cs);
4030-
}
40314003
}
40324004

40334005
return 0;

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