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66 | 66 | #endif
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67 | 67 |
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68 | 68 | /* AArch32 CPSR bits, as seen in AArch32 */
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69 |
| -#define COMPAT_PSR_MODE_MASK 0x0000001f |
70 |
| -#define COMPAT_PSR_MODE_USR 0x00000010 |
71 |
| -#define COMPAT_PSR_MODE_FIQ 0x00000011 |
72 |
| -#define COMPAT_PSR_MODE_IRQ 0x00000012 |
73 |
| -#define COMPAT_PSR_MODE_SVC 0x00000013 |
74 |
| -#define COMPAT_PSR_MODE_ABT 0x00000017 |
75 |
| -#define COMPAT_PSR_MODE_HYP 0x0000001a |
76 |
| -#define COMPAT_PSR_MODE_UND 0x0000001b |
77 |
| -#define COMPAT_PSR_MODE_SYS 0x0000001f |
78 |
| -#define COMPAT_PSR_T_BIT 0x00000020 |
79 |
| -#define COMPAT_PSR_F_BIT 0x00000040 |
80 |
| -#define COMPAT_PSR_I_BIT 0x00000080 |
81 |
| -#define COMPAT_PSR_A_BIT 0x00000100 |
82 |
| -#define COMPAT_PSR_E_BIT 0x00000200 |
83 | 69 | #define COMPAT_PSR_DIT_BIT 0x00200000
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84 |
| -#define COMPAT_PSR_J_BIT 0x01000000 |
85 |
| -#define COMPAT_PSR_Q_BIT 0x08000000 |
86 |
| -#define COMPAT_PSR_V_BIT 0x10000000 |
87 |
| -#define COMPAT_PSR_C_BIT 0x20000000 |
88 |
| -#define COMPAT_PSR_Z_BIT 0x40000000 |
89 |
| -#define COMPAT_PSR_N_BIT 0x80000000 |
90 |
| -#define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ |
91 |
| -#define COMPAT_PSR_GE_MASK 0x000f0000 |
92 |
| - |
93 |
| -#ifdef CONFIG_CPU_BIG_ENDIAN |
94 |
| -#define COMPAT_PSR_ENDSTATE COMPAT_PSR_E_BIT |
95 |
| -#else |
96 |
| -#define COMPAT_PSR_ENDSTATE 0 |
97 |
| -#endif |
98 | 70 |
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99 | 71 | /*
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100 | 72 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
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