driver: mmc: octeontx2: Fix tuning for T96 C0

Need to enable and disable emmc clock when updating timing
parameters in T96 C0.

Change-Id: I8d34918b961d9b466eb2b7465a6fb2610dd6acdc
Signed-off-by: Chandrakala Chavva <[email protected]>
Reviewed-on: https://sj1git1.cavium.com/21284
Reviewed-by: Chandrakala Chavva <[email protected]>
Tested-by: sa_ip-sw-jenkins <[email protected]>
Reviewed-on: https://sj1git1.cavium.com/23928
Reviewed-by: Sunil Kovvuri Goutham <[email protected]>
Reviewed-on: https://sj1git1.cavium.com/24028
Tested-by: Sunil Kovvuri Goutham <[email protected]>

Jira: LINUX-4695
Orabug: 30969935

Signed-off-by: Dave Kleikamp <[email protected]>
Reviewed-by: Karl Volz <[email protected]>
Signed-off-by: Somasundaram Krishnasamy <[email protected]>

Author: Chandrakala Chavva

drivers/mmc/host/cavium-thunderx.c

@@ -72,7 +72,7 @@ void thunder_calibrate_mmc(struct cvm_mmc_host *host)
 	if (is_mmc_otx2_A0(host) || is_mmc_95xx(host))
 		writeq(1, host->base + MIO_EMM_DEBUG(host));
 
-	if (is_mmc_otx2_A0(host)) {
+	if (is_mmc_otx2_A0(host) || is_mmc_otx2_C0(host)) {
 		/*
 		 * Operation of up to 100 MHz may be achieved by skipping the
 		 * steps that establish the tap delays and instead assuming
@@ -150,7 +150,6 @@ void thunder_calibrate_mmc(struct cvm_mmc_host *host)
 		writeq(emm_switch, host->base + MIO_EMM_SWITCH(host));
 		writeq(emm_io_ctl, host->base + MIO_EMM_IO_CTL(host));
 		mdelay(1);
-
 	}
 
 	/*

drivers/mmc/host/cavium.c

@@ -148,12 +148,46 @@ bool cvm_is_mmc_timing_ddr(struct cvm_mmc_slot *slot)
 		return false;
 }
 
+static void cvm_mmc_clk_config(struct cvm_mmc_host *host, bool flag)
+{
+	u64 emm_debug;
+
+	if (!is_mmc_otx2_C0(host))
+		return;
+
+	/* Turn off the clock */
+	if (flag) {
+		emm_debug = readq(host->base + MIO_EMM_DEBUG(host));
+		emm_debug |= MIO_EMM_DEBUG_CLK_DIS;
+		writeq(emm_debug, host->base + MIO_EMM_DEBUG(host));
+		udelay(1);
+		emm_debug = readq(host->base + MIO_EMM_DEBUG(host));
+		emm_debug |= MIO_EMM_DEBUG_RDSYNC;
+		writeq(emm_debug, host->base + MIO_EMM_DEBUG(host));
+		udelay(1);
+	} else {
+		/* Turn on the clock */
+		emm_debug = readq(host->base + MIO_EMM_DEBUG(host));
+		emm_debug &= MIO_EMM_DEBUG_RDSYNC;
+		writeq(emm_debug, host->base + MIO_EMM_DEBUG(host));
+		udelay(1);
+		emm_debug = readq(host->base + MIO_EMM_DEBUG(host));
+		emm_debug &= MIO_EMM_DEBUG_CLK_DIS;
+		writeq(emm_debug, host->base + MIO_EMM_DEBUG(host));
+		udelay(1);
+	}
+}
+
 static void cvm_mmc_set_timing(struct cvm_mmc_slot *slot)
 {
-	if (is_mmc_8xxx(slot->host))
+	struct cvm_mmc_host *host = slot->host;
+
+	if (is_mmc_8xxx(host))
 		return;
 
-	writeq(slot->taps, slot->host->base + MIO_EMM_TIMING(slot->host));
+	cvm_mmc_clk_config(host, CLK_OFF);
+	writeq(slot->taps, host->base + MIO_EMM_TIMING(host));
+	cvm_mmc_clk_config(host, CLK_ON);
 }
 
 static int tout(struct cvm_mmc_slot *slot, int ps, int hint)
@@ -1328,11 +1362,13 @@ static int adjust_tuning(struct mmc_host *mmc, struct adj *adj, u32 opcode)
 	/* loop over range+1 to simplify processing */
 	for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
 		if (tap < MAX_NO_OF_TAPS) {
+			cvm_mmc_clk_config(host, CLK_OFF);
 			timing = readq(host->base + MIO_EMM_TIMING(host));
 			timing &= ~adj->mask;
 			timing |= (tap << __bf_shf(adj->mask));
 			writeq(timing, host->base + MIO_EMM_TIMING(host));
 
+			cvm_mmc_clk_config(host, CLK_ON);
 			err = adj->test(mmc, NULL, opcode);
 
 			how[tap] = "-+"[!err];

drivers/mmc/host/cavium.h

@@ -59,6 +59,10 @@
 #define PS_400			(400)
 #define MAX_NO_OF_TAPS		64
 
+/* Macros to enable/disable clks */
+#define CLK_ON			0
+#define CLK_OFF			1
+
 
 /* DMA register addresses */
 #define MIO_EMM_DMA_FIFO_CFG(x)	(0x00 + x->reg_off_dma)
@@ -288,6 +292,8 @@ struct cvm_mmc_cr_mods {
 #define MIO_EMM_SWITCH_CLK		GENMASK_ULL(31, 0)
 #define MIO_EMM_SWITCH_CLK_HI		GENMASK_ULL(31, 16)
 #define MIO_EMM_SWITCH_CLK_LO		GENMASK_ULL(15, 0)
+#define MIO_EMM_DEBUG_CLK_DIS		BIT_ULL(20)
+#define MIO_EMM_DEBUG_RDSYNC		BIT_ULL(21)
 
 /* Protoypes */
 irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id);