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Merge Tegra clk changes into next/dt64
These are a prerequisite to some of the tegra DT changes, and got merged as part of tegra-for-4.8-clk into clk-next. * commit 'e452b818db48': clk: tegra: Enable sor1 and sor1_src on Tegra210 clk: tegra: Squash sor1 safe/brick/src into a single mux clk: tegra: Disable spread spectrum on pll_d2 clk: tegra: Fixup post dividers on Tegra210
2 parents 17ef34e + e452b81 commit 77938a9

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4 files changed

+65
-62
lines changed

4 files changed

+65
-62
lines changed

‎drivers/clk/tegra/clk-id.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,6 @@ enum clk_id {
238238
tegra_clk_sor0,
239239
tegra_clk_sor0_lvds,
240240
tegra_clk_sor1,
241-
tegra_clk_sor1_brick,
242241
tegra_clk_sor1_src,
243242
tegra_clk_spdif,
244243
tegra_clk_spdif_2x,

‎drivers/clk/tegra/clk-tegra-periph.c

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -594,15 +594,17 @@ static u32 mux_pllp_plld_plld2_clkm_idx[] = {
594594
[0] = 0, [1] = 2, [2] = 5, [3] = 6
595595
};
596596

597-
static const char *mux_plldp_sor1_src[] = {
598-
"pll_dp", "clk_sor1_src"
599-
};
600-
#define mux_plldp_sor1_src_idx NULL
601-
602-
static const char *mux_clkm_sor1_brick_sor1_src[] = {
603-
"clk_m", "sor1_brick", "sor1_src", "sor1_brick"
604-
};
605-
#define mux_clkm_sor1_brick_sor1_src_idx NULL
597+
static const char *mux_sor_safe_sor1_brick_sor1_src[] = {
598+
/*
599+
* Bit 0 of the mux selects sor1_brick, irrespective of bit 1, so the
600+
* sor1_brick parent appears twice in the list below. This is merely
601+
* to support clk_get_parent() if firmware happened to set these bits
602+
* to 0b11. While not an invalid setting, code should always set the
603+
* bits to 0b01 to select sor1_brick.
604+
*/
605+
"sor_safe", "sor1_brick", "sor1_src", "sor1_brick"
606+
};
607+
#define mux_sor_safe_sor1_brick_sor1_src_idx NULL
606608

607609
static const char *mux_pllp_pllre_clkm[] = {
608610
"pll_p", "pll_re_out1", "clk_m"
@@ -778,8 +780,7 @@ static struct tegra_periph_init_data periph_clks[] = {
778780
MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
779781
MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
780782
MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
781-
NODIV("sor1_brick", mux_plldp_sor1_src, CLK_SOURCE_SOR1, 14, MASK(1), 183, 0, tegra_clk_sor1_brick, &sor1_lock),
782-
NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
783+
NODIV("sor1", mux_sor_safe_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 14, MASK(2), 183, 0, tegra_clk_sor1, &sor1_lock),
783784
MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
784785
MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
785786
I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),

‎drivers/clk/tegra/clk-tegra210.c

Lines changed: 52 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -1366,9 +1366,9 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
13661366

13671367
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
13681368
/* 1 GHz */
1369-
{ 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */
1370-
{ 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */
1371-
{ 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */
1369+
{ 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1370+
{ 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1371+
{ 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
13721372
{ 0, 0, 0, 0, 0, 0 },
13731373
};
13741374

@@ -1417,9 +1417,9 @@ static struct div_nmp pllc_nmp = {
14171417
};
14181418

14191419
static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1420-
{ 12000000, 510000000, 85, 1, 1, 0 },
1421-
{ 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */
1422-
{ 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */
1420+
{ 12000000, 510000000, 85, 1, 2, 0 },
1421+
{ 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1422+
{ 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
14231423
{ 0, 0, 0, 0, 0, 0 },
14241424
};
14251425

@@ -1532,9 +1532,9 @@ static struct div_nmp pllss_nmp = {
15321532
};
15331533

15341534
static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1535-
{ 12000000, 600000000, 50, 1, 0, 0 },
1536-
{ 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */
1537-
{ 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */
1535+
{ 12000000, 600000000, 50, 1, 1, 0 },
1536+
{ 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1537+
{ 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
15381538
{ 0, 0, 0, 0, 0, 0 },
15391539
};
15401540

@@ -1583,19 +1583,19 @@ static struct tegra_clk_pll_params pll_c4_vco_params = {
15831583
};
15841584

15851585
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1586-
{ 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */
1587-
{ 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */
1588-
{ 38400000, 297600000, 93, 4, 2, 0 },
1589-
{ 38400000, 400000000, 125, 4, 2, 0 },
1590-
{ 38400000, 532800000, 111, 4, 1, 0 },
1591-
{ 38400000, 665600000, 104, 3, 1, 0 },
1592-
{ 38400000, 800000000, 125, 3, 1, 0 },
1593-
{ 38400000, 931200000, 97, 4, 0, 0 },
1594-
{ 38400000, 1065600000, 111, 4, 0, 0 },
1595-
{ 38400000, 1200000000, 125, 4, 0, 0 },
1596-
{ 38400000, 1331200000, 104, 3, 0, 0 },
1597-
{ 38400000, 1459200000, 76, 2, 0, 0 },
1598-
{ 38400000, 1600000000, 125, 3, 0, 0 },
1586+
{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1587+
{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1588+
{ 38400000, 297600000, 93, 4, 3, 0 },
1589+
{ 38400000, 400000000, 125, 4, 3, 0 },
1590+
{ 38400000, 532800000, 111, 4, 2, 0 },
1591+
{ 38400000, 665600000, 104, 3, 2, 0 },
1592+
{ 38400000, 800000000, 125, 3, 2, 0 },
1593+
{ 38400000, 931200000, 97, 4, 1, 0 },
1594+
{ 38400000, 1065600000, 111, 4, 1, 0 },
1595+
{ 38400000, 1200000000, 125, 4, 1, 0 },
1596+
{ 38400000, 1331200000, 104, 3, 1, 0 },
1597+
{ 38400000, 1459200000, 76, 2, 1, 0 },
1598+
{ 38400000, 1600000000, 125, 3, 1, 0 },
15991599
{ 0, 0, 0, 0, 0, 0 },
16001600
};
16011601

@@ -1705,9 +1705,9 @@ static struct tegra_clk_pll_params pll_e_params = {
17051705
};
17061706

17071707
static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1708-
{ 12000000, 672000000, 56, 1, 0, 0 },
1709-
{ 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */
1710-
{ 38400000, 672000000, 70, 4, 0, 0 },
1708+
{ 12000000, 672000000, 56, 1, 1, 0 },
1709+
{ 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1710+
{ 38400000, 672000000, 70, 4, 1, 0 },
17111711
{ 0, 0, 0, 0, 0, 0 },
17121712
};
17131713

@@ -1754,8 +1754,8 @@ static struct div_nmp pllp_nmp = {
17541754
};
17551755

17561756
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1757-
{ 12000000, 408000000, 34, 1, 0, 0 },
1758-
{ 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */
1757+
{ 12000000, 408000000, 34, 1, 1, 0 },
1758+
{ 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
17591759
{ 0, 0, 0, 0, 0, 0 },
17601760
};
17611761

@@ -1820,14 +1820,14 @@ static struct div_nmp plla_nmp = {
18201820
};
18211821

18221822
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
1823-
{ 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */
1824-
{ 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */
1825-
{ 12000000, 240000000, 60, 1, 2, 1, 0 },
1826-
{ 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */
1827-
{ 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */
1828-
{ 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */
1829-
{ 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */
1830-
{ 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */
1823+
{ 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
1824+
{ 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
1825+
{ 12000000, 240000000, 60, 1, 3, 1, 0 },
1826+
{ 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
1827+
{ 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
1828+
{ 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
1829+
{ 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
1830+
{ 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
18311831
{ 38400000, 240000000, 75, 3, 3, 1, 0 },
18321832
{ 0, 0, 0, 0, 0, 0, 0 },
18331833
};
@@ -1873,9 +1873,9 @@ static struct div_nmp plld_nmp = {
18731873
};
18741874

18751875
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
1876-
{ 12000000, 594000000, 99, 1, 1, 0, 0 },
1877-
{ 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1878-
{ 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1876+
{ 12000000, 594000000, 99, 1, 2, 0, 0 },
1877+
{ 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
1878+
{ 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
18791879
{ 0, 0, 0, 0, 0, 0, 0 },
18801880
};
18811881

@@ -1911,9 +1911,9 @@ static struct tegra_clk_pll_params pll_d_params = {
19111911
};
19121912

19131913
static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
1914-
{ 12000000, 594000000, 99, 1, 1, 0, 0xf000 },
1915-
{ 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1916-
{ 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1914+
{ 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
1915+
{ 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
1916+
{ 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
19171917
{ 0, 0, 0, 0, 0, 0, 0 },
19181918
};
19191919

@@ -1935,8 +1935,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
19351935
.sdm_din_mask = PLLA_SDM_DIN_MASK,
19361936
.sdm_ctrl_reg = PLLD2_MISC1,
19371937
.sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
1938-
.ssc_ctrl_reg = PLLD2_MISC1,
1939-
.ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK,
1938+
/* disable spread-spectrum for pll_d2 */
1939+
.ssc_ctrl_reg = 0,
1940+
.ssc_ctrl_en_mask = 0,
19401941
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
19411942
.pdiv_tohw = pll_qlin_pdiv_to_hw,
19421943
.div_nmp = &pllss_nmp,
@@ -1955,9 +1956,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
19551956
};
19561957

19571958
static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
1958-
{ 12000000, 270000000, 90, 1, 3, 0, 0xf000 },
1959-
{ 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */
1960-
{ 38400000, 270000000, 28, 1, 3, 0, 0xf400 },
1959+
{ 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
1960+
{ 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
1961+
{ 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
19611962
{ 0, 0, 0, 0, 0, 0, 0 },
19621963
};
19631964

@@ -2007,9 +2008,9 @@ static struct div_nmp pllu_nmp = {
20072008
};
20082009

20092010
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2010-
{ 12000000, 480000000, 40, 1, 0, 0 },
2011-
{ 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
2012-
{ 38400000, 480000000, 25, 2, 0, 0 },
2011+
{ 12000000, 480000000, 40, 1, 1, 0 },
2012+
{ 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2013+
{ 38400000, 480000000, 25, 2, 1, 0 },
20132014
{ 0, 0, 0, 0, 0, 0 },
20142015
};
20152016

@@ -2154,6 +2155,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
21542155
[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
21552156
[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
21562157
[tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2158+
[tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2159+
[tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
21572160
[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
21582161
[tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
21592162
[tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },

‎include/dt-bindings/clock/tegra210-car.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -308,7 +308,7 @@
308308
#define TEGRA210_CLK_CLK_OUT_3 279
309309
#define TEGRA210_CLK_BLINK 280
310310
/* 281 */
311-
/* 282 */
311+
#define TEGRA210_CLK_SOR1_SRC 282
312312
/* 283 */
313313
#define TEGRA210_CLK_XUSB_HOST_SRC 284
314314
#define TEGRA210_CLK_XUSB_FALCON_SRC 285

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