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Ivan Mikhaylovmpe
Ivan Mikhaylov
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mpe
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powerpc/44x/fsp2: Add irq error handlers
Add irq error handlers for cmu, plb, opb, mcue, conf with debug information output in case of problems. Signed-off-by: Ivan Mikhaylov <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
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  • arch/powerpc/platforms/44x

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‎arch/powerpc/platforms/44x/fsp2.c

Lines changed: 204 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,212 @@
2828
#include <asm/uic.h>
2929
#include <asm/ppc4xx.h>
3030
#include <asm/dcr.h>
31+
#include <linux/interrupt.h>
32+
#include <linux/of_irq.h>
3133
#include "fsp2.h"
3234

35+
#define FSP2_BUS_ERR "ibm,bus-error-irq"
36+
#define FSP2_CMU_ERR "ibm,cmu-error-irq"
37+
#define FSP2_CONF_ERR "ibm,conf-error-irq"
38+
#define FSP2_OPBD_ERR "ibm,opbd-error-irq"
39+
#define FSP2_MCUE "ibm,mc-ue-irq"
40+
#define FSP2_RST_WRN "ibm,reset-warning-irq"
41+
3342
static __initdata struct of_device_id fsp2_of_bus[] = {
3443
{ .compatible = "ibm,plb4", },
3544
{ .compatible = "ibm,plb6", },
3645
{ .compatible = "ibm,opb", },
3746
{},
3847
};
3948

49+
static void l2regs(void)
50+
{
51+
pr_err("L2 Controller:\n");
52+
pr_err("MCK: 0x%08x\n", mfl2(L2MCK));
53+
pr_err("INT: 0x%08x\n", mfl2(L2INT));
54+
pr_err("PLBSTAT0: 0x%08x\n", mfl2(L2PLBSTAT0));
55+
pr_err("PLBSTAT1: 0x%08x\n", mfl2(L2PLBSTAT1));
56+
pr_err("ARRSTAT0: 0x%08x\n", mfl2(L2ARRSTAT0));
57+
pr_err("ARRSTAT1: 0x%08x\n", mfl2(L2ARRSTAT1));
58+
pr_err("ARRSTAT2: 0x%08x\n", mfl2(L2ARRSTAT2));
59+
pr_err("CPUSTAT: 0x%08x\n", mfl2(L2CPUSTAT));
60+
pr_err("RACSTAT0: 0x%08x\n", mfl2(L2RACSTAT0));
61+
pr_err("WACSTAT0: 0x%08x\n", mfl2(L2WACSTAT0));
62+
pr_err("WACSTAT1: 0x%08x\n", mfl2(L2WACSTAT1));
63+
pr_err("WACSTAT2: 0x%08x\n", mfl2(L2WACSTAT2));
64+
pr_err("WDFSTAT: 0x%08x\n", mfl2(L2WDFSTAT));
65+
pr_err("LOG0: 0x%08x\n", mfl2(L2LOG0));
66+
pr_err("LOG1: 0x%08x\n", mfl2(L2LOG1));
67+
pr_err("LOG2: 0x%08x\n", mfl2(L2LOG2));
68+
pr_err("LOG3: 0x%08x\n", mfl2(L2LOG3));
69+
pr_err("LOG4: 0x%08x\n", mfl2(L2LOG4));
70+
pr_err("LOG5: 0x%08x\n", mfl2(L2LOG5));
71+
}
72+
73+
static void show_plbopb_regs(u32 base, int num)
74+
{
75+
pr_err("\nPLBOPB Bridge %d:\n", num);
76+
pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0));
77+
pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1));
78+
pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2));
79+
pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU));
80+
pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR));
81+
}
82+
83+
static irqreturn_t bus_err_handler(int irq, void *data)
84+
{
85+
pr_err("Bus Error\n");
86+
87+
l2regs();
88+
89+
pr_err("\nPLB6 Controller:\n");
90+
pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD));
91+
pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR));
92+
93+
pr_err("\nPLB6-to-PLB4 Bridge:\n");
94+
pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR));
95+
pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH));
96+
pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL));
97+
98+
pr_err("\nPLB4-to-PLB6 Bridge:\n");
99+
pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_ESR));
100+
pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARH));
101+
pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARL));
102+
103+
pr_err("\nPLB6-to-MCIF Bridge:\n");
104+
pr_err("BESR0: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR0));
105+
pr_err("BESR1: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR1));
106+
pr_err("BEARH: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARH));
107+
pr_err("BEARL: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARL));
108+
109+
pr_err("\nPLB4 Arbiter:\n");
110+
pr_err("P0ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRH));
111+
pr_err("P0ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRL));
112+
pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));
113+
pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));
114+
pr_err("P1ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRH));
115+
pr_err("P1ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRL));
116+
pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));
117+
pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));
118+
119+
show_plbopb_regs(DCRN_PLB4OPB0_BASE, 0);
120+
show_plbopb_regs(DCRN_PLB4OPB1_BASE, 1);
121+
show_plbopb_regs(DCRN_PLB4OPB2_BASE, 2);
122+
show_plbopb_regs(DCRN_PLB4OPB3_BASE, 3);
123+
124+
pr_err("\nPLB4-to-AHB Bridge:\n");
125+
pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_ESR));
126+
pr_err("SEUAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SEUAR));
127+
pr_err("SELAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SELAR));
128+
129+
pr_err("\nAHB-to-PLB4 Bridge:\n");
130+
pr_err("\nESR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_ESR));
131+
pr_err("\nEAR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_EAR));
132+
panic("Bus Error\n");
133+
}
134+
135+
static irqreturn_t cmu_err_handler(int irq, void *data) {
136+
pr_err("CMU Error\n");
137+
pr_err("FIR0: 0x%08x\n", mfcmu(CMUN_FIR0));
138+
panic("CMU Error\n");
139+
}
140+
141+
static irqreturn_t conf_err_handler(int irq, void *data) {
142+
pr_err("Configuration Logic Error\n");
143+
pr_err("CONF_FIR: 0x%08x\n", mfdcr(DCRN_CONF_FIR_RWC));
144+
pr_err("RPERR0: 0x%08x\n", mfdcr(DCRN_CONF_RPERR0));
145+
pr_err("RPERR1: 0x%08x\n", mfdcr(DCRN_CONF_RPERR1));
146+
panic("Configuration Logic Error\n");
147+
}
148+
149+
static irqreturn_t opbd_err_handler(int irq, void *data) {
150+
panic("OPBD Error\n");
151+
}
152+
153+
static irqreturn_t mcue_handler(int irq, void *data) {
154+
pr_err("DDR: Uncorrectable Error\n");
155+
pr_err("MCSTAT: 0x%08x\n",
156+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT));
157+
pr_err("MCOPT1: 0x%08x\n",
158+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT1));
159+
pr_err("MCOPT2: 0x%08x\n",
160+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT2));
161+
pr_err("PHYSTAT: 0x%08x\n",
162+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_PHYSTAT));
163+
pr_err("CFGR0: 0x%08x\n",
164+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0));
165+
pr_err("CFGR1: 0x%08x\n",
166+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1));
167+
pr_err("CFGR2: 0x%08x\n",
168+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2));
169+
pr_err("CFGR3: 0x%08x\n",
170+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3));
171+
pr_err("SCRUB_CNTL: 0x%08x\n",
172+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_SCRUB_CNTL));
173+
pr_err("ECCERR_PORT0: 0x%08x\n",
174+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_PORT0));
175+
pr_err("ECCERR_ADDR_PORT0: 0x%08x\n",
176+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_ADDR_PORT0));
177+
pr_err("ECCERR_CNT_PORT0: 0x%08x\n",
178+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_COUNT_PORT0));
179+
pr_err("ECC_CHECK_PORT0: 0x%08x\n",
180+
mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECC_CHECK_PORT0));
181+
pr_err("MCER0: 0x%08x\n",
182+
mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0));
183+
pr_err("MCER1: 0x%08x\n",
184+
mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1));
185+
pr_err("BESR: 0x%08x\n",
186+
mfdcr(DCRN_PLB6MCIF_BESR0));
187+
pr_err("BEARL: 0x%08x\n",
188+
mfdcr(DCRN_PLB6MCIF_BEARL));
189+
pr_err("BEARH: 0x%08x\n",
190+
mfdcr(DCRN_PLB6MCIF_BEARH));
191+
panic("DDR: Uncorrectable Error\n");
192+
}
193+
194+
static irqreturn_t rst_wrn_handler(int irq, void *data) {
195+
u32 crcs = mfcmu(CMUN_CRCS);
196+
switch (crcs & CRCS_STAT_MASK) {
197+
case CRCS_STAT_CHIP_RST_B:
198+
panic("Received chassis-initiated reset request");
199+
default:
200+
panic("Unknown external reset: CRCS=0x%x", crcs);
201+
}
202+
}
203+
204+
static void node_irq_request(const char *compat, irq_handler_t errirq_handler)
205+
{
206+
struct device_node *np;
207+
unsigned int irq;
208+
int32_t rc;
209+
210+
for_each_compatible_node(np, NULL, compat) {
211+
irq = irq_of_parse_and_map(np, 0);
212+
if (irq == NO_IRQ) {
213+
pr_err("device tree node %s is missing a interrupt",
214+
np->name);
215+
return;
216+
}
217+
218+
rc = request_irq(irq, errirq_handler, 0, np->name, np);
219+
if (rc) {
220+
pr_err("fsp_of_probe: request_irq failed: np=%s rc=%d",
221+
np->full_name, rc);
222+
return;
223+
}
224+
}
225+
}
226+
227+
static void critical_irq_setup(void)
228+
{
229+
node_irq_request(FSP2_CMU_ERR, cmu_err_handler);
230+
node_irq_request(FSP2_BUS_ERR, bus_err_handler);
231+
node_irq_request(FSP2_CONF_ERR, conf_err_handler);
232+
node_irq_request(FSP2_OPBD_ERR, opbd_err_handler);
233+
node_irq_request(FSP2_MCUE, mcue_handler);
234+
node_irq_request(FSP2_RST_WRN, rst_wrn_handler);
235+
}
236+
40237
static int __init fsp2_device_probe(void)
41238
{
42239
of_platform_bus_probe(NULL, fsp2_of_bus, NULL);
@@ -105,11 +302,17 @@ static int __init fsp2_probe(void)
105302
return 1;
106303
}
107304

305+
static void __init fsp2_irq_init(void)
306+
{
307+
uic_init_tree();
308+
critical_irq_setup();
309+
}
310+
108311
define_machine(fsp2) {
109312
.name = "FSP-2",
110313
.probe = fsp2_probe,
111314
.progress = udbg_progress,
112-
.init_IRQ = uic_init_tree,
315+
.init_IRQ = fsp2_irq_init,
113316
.get_irq = uic_get_irq,
114317
.restart = ppc4xx_reset_system,
115318
.calibrate_decr = generic_calibrate_decr,

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