@@ -59,10 +59,6 @@ static u32 nodes_per_socket = 1;
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#define AMD_MODEL_RANGE_START (range ) (((range) >> 12) & 0xfff)
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#define AMD_MODEL_RANGE_END (range ) ((range) & 0xfff)
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- static const int amd_erratum_1485 [] =
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- AMD_LEGACY_ERRATUM (AMD_MODEL_RANGE (0x19 , 0x10 , 0x0 , 0x1f , 0xf ),
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- AMD_MODEL_RANGE (0x19 , 0x60 , 0x0 , 0xaf , 0xf ));
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-
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static bool cpu_has_amd_erratum (struct cpuinfo_x86 * cpu , const int * erratum )
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{
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int osvw_id = * erratum ++ ;
@@ -1093,6 +1089,9 @@ static void init_amd_zen3(struct cpuinfo_x86 *c)
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static void init_amd_zen4 (struct cpuinfo_x86 * c )
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{
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init_amd_zen_common ();
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+
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+ if (!cpu_has (c , X86_FEATURE_HYPERVISOR ))
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+ msr_set_bit (MSR_ZEN4_BP_CFG , MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT );
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}
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static void init_amd (struct cpuinfo_x86 * c )
@@ -1216,10 +1215,6 @@ static void init_amd(struct cpuinfo_x86 *c)
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cpu_has (c , X86_FEATURE_AUTOIBRS ))
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WARN_ON_ONCE (msr_set_bit (MSR_EFER , _EFER_AUTOIBRS ));
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- if (!cpu_has (c , X86_FEATURE_HYPERVISOR ) &&
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- cpu_has_amd_erratum (c , amd_erratum_1485 ))
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- msr_set_bit (MSR_ZEN4_BP_CFG , MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT );
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-
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/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
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clear_cpu_cap (c , X86_FEATURE_APIC_MSRS_FENCE );
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}
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