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Qingqing Zhuoalexdeucher
Qingqing Zhuo
authored and
alexdeucher
committed
drm/amd/display: Introduce DML2
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Co-developed-by: Roman Li <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent 6e2c494 commit 7966f31

36 files changed

+19572
-4
lines changed

‎drivers/gpu/drm/amd/display/dc/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,8 @@ ifdef CONFIG_DRM_AMD_DC_FP
2828

2929
KCOV_INSTRUMENT := n
3030

31-
DC_LIBS += dcn20
3231
DC_LIBS += dcn10
32+
DC_LIBS += dcn20
3333
DC_LIBS += dcn21
3434
DC_LIBS += dcn201
3535
DC_LIBS += dcn30
@@ -44,6 +44,7 @@ DC_LIBS += dcn32
4444
DC_LIBS += dcn321
4545
DC_LIBS += dcn35
4646
DC_LIBS += dml
47+
DC_LIBS += dml2
4748
endif
4849

4950
DC_LIBS += dce120

‎drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,8 @@
7777

7878
#include "hw_sequencer_private.h"
7979

80+
#include "dml2/dml2_internal_types.h"
81+
8082
#include "dce/dmub_outbox.h"
8183

8284
#define CTX \
@@ -2176,6 +2178,11 @@ struct dc_state *dc_create_state(struct dc *dc)
21762178

21772179
init_state(dc, context);
21782180

2181+
#ifdef CONFIG_DRM_AMD_DC_FP
2182+
if (dc->debug.using_dml2) {
2183+
dml2_create(dc, &dc->dml2_options, &context->bw_ctx.dml2);
2184+
}
2185+
#endif
21792186
kref_init(&context->refcount);
21802187

21812188
return context;
@@ -2185,11 +2192,25 @@ struct dc_state *dc_copy_state(struct dc_state *src_ctx)
21852192
{
21862193
int i, j;
21872194
struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
2195+
#ifdef CONFIG_DRM_AMD_DC_FP
2196+
struct dml2_context *dml2 = NULL;
2197+
#endif
21882198

21892199
if (!new_ctx)
21902200
return NULL;
21912201
memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
21922202

2203+
#ifdef CONFIG_DRM_AMD_DC_FP
2204+
if (new_ctx->bw_ctx.dml2) {
2205+
dml2 = kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
2206+
if (!dml2)
2207+
return NULL;
2208+
2209+
memcpy(dml2, src_ctx->bw_ctx.dml2, sizeof(struct dml2_context));
2210+
new_ctx->bw_ctx.dml2 = dml2;
2211+
}
2212+
#endif
2213+
21932214
for (i = 0; i < MAX_PIPES; i++) {
21942215
struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
21952216

@@ -2228,6 +2249,12 @@ static void dc_state_free(struct kref *kref)
22282249
{
22292250
struct dc_state *context = container_of(kref, struct dc_state, refcount);
22302251
dc_resource_state_destruct(context);
2252+
2253+
#ifdef CONFIG_DRM_AMD_DC_FP
2254+
dml2_destroy(context->bw_ctx.dml2);
2255+
context->bw_ctx.dml2 = 0;
2256+
#endif
2257+
22312258
kvfree(context);
22322259
}
22332260

@@ -4679,6 +4706,9 @@ bool dc_set_power_state(
46794706
{
46804707
struct kref refcount;
46814708
struct display_mode_lib *dml;
4709+
#ifdef CONFIG_DRM_AMD_DC_FP
4710+
struct dml2_context *dml2 = NULL;
4711+
#endif
46824712

46834713
if (!dc->current_state)
46844714
return true;
@@ -4698,6 +4728,10 @@ bool dc_set_power_state(
46984728

46994729
break;
47004730
default:
4731+
#ifdef CONFIG_DRM_AMD_DC_FP
4732+
if (dc->debug.using_dml2)
4733+
dml2 = dc->current_state->bw_ctx.dml2;
4734+
#endif
47014735
ASSERT(dc->current_state->stream_count == 0);
47024736
/* Zero out the current context so that on resume we start with
47034737
* clean state, and dc hw programming optimizations will not
@@ -4724,6 +4758,11 @@ bool dc_set_power_state(
47244758

47254759
kfree(dml);
47264760

4761+
#ifdef CONFIG_DRM_AMD_DC_FP
4762+
if (dc->debug.using_dml2)
4763+
dc->current_state->bw_ctx.dml2 = dml2;
4764+
#endif
4765+
47274766
break;
47284767
}
47294768

‎drivers/gpu/drm/amd/display/dc/core/dc_resource.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@
4141
#include "dpcd_defs.h"
4242
#include "link_enc_cfg.h"
4343
#include "link.h"
44+
#include "clk_mgr.h"
4445
#include "virtual/virtual_link_hwss.h"
4546
#include "link/hwss/link_hwss_dio.h"
4647
#include "link/hwss/link_hwss_dpia.h"
@@ -86,6 +87,8 @@
8687
dc->ctx->logger
8788
#define DC_LOGGER_INIT(logger)
8889

90+
#include "dml2/dml2_wrapper.h"
91+
8992
#define UNABLE_TO_SPLIT -1
9093

9194
enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
@@ -318,6 +321,10 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
318321
res_pool->ref_clocks.xtalin_clock_inKhz;
319322
res_pool->ref_clocks.dchub_ref_clock_inKhz =
320323
res_pool->ref_clocks.xtalin_clock_inKhz;
324+
if ((res_pool->hubbub->funcs->get_dchub_ref_freq))
325+
res_pool->hubbub->funcs->get_dchub_ref_freq(res_pool->hubbub,
326+
res_pool->ref_clocks.dccg_ref_clock_inKhz,
327+
&res_pool->ref_clocks.dchub_ref_clock_inKhz);
321328
} else
322329
ASSERT_CRITICAL(false);
323330
}
@@ -4358,9 +4365,22 @@ void dc_resource_state_copy_construct(
43584365
{
43594366
int i, j;
43604367
struct kref refcount = dst_ctx->refcount;
4368+
#ifdef CONFIG_DRM_AMD_DC_FP
4369+
struct dml2_context *dml2 = NULL;
4370+
4371+
// Need to preserve allocated dml2 context
4372+
if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2)
4373+
dml2 = dst_ctx->bw_ctx.dml2;
4374+
#endif
43614375

43624376
*dst_ctx = *src_ctx;
43634377

4378+
#ifdef CONFIG_DRM_AMD_DC_FP
4379+
// Preserve allocated dml2 context
4380+
if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2)
4381+
dst_ctx->bw_ctx.dml2 = dml2;
4382+
#endif
4383+
43644384
for (i = 0; i < MAX_PIPES; i++) {
43654385
struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
43664386

‎drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@
4040
#include "inc/hw/dmcu.h"
4141
#include "dml/display_mode_lib.h"
4242

43+
#include "dml2/dml2_wrapper.h"
44+
4345
struct abm_save_restore;
4446

4547
/* forward declaration */
@@ -942,6 +944,7 @@ struct dc_debug_options {
942944
bool dml_disallow_alternate_prefetch_modes;
943945
bool use_legacy_soc_bb_mechanism;
944946
bool exit_idle_opt_for_cursor_updates;
947+
bool using_dml2;
945948
bool enable_single_display_2to1_odm_policy;
946949
bool enable_double_buffered_dsc_pg_support;
947950
bool enable_dp_dig_pixel_rate_div_policy;
@@ -1049,6 +1052,8 @@ struct dc {
10491052
struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
10501053
} update_bw_bounding_box;
10511054
} scratch;
1055+
1056+
struct dml2_configuration_options dml2_options;
10521057
};
10531058

10541059
enum frame_buffer_mode {

‎drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

Lines changed: 58 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,8 @@
8989
#include "dcn20/dcn20_vmid.h"
9090
#include "dml/dcn32/dcn32_fpu.h"
9191

92+
#include "dml2/dml2_wrapper.h"
93+
9294
#define DC_LOGGER_INIT(logger)
9395

9496
enum dcn32_clk_src_array_id {
@@ -714,6 +716,7 @@ static const struct dc_debug_options debug_defaults_drv = {
714716
.use_max_lb = true,
715717
.force_disable_subvp = false,
716718
.exit_idle_opt_for_cursor_updates = true,
719+
.using_dml2 = false,
717720
.enable_single_display_2to1_odm_policy = true,
718721

719722
/* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
@@ -1805,9 +1808,7 @@ void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
18051808
}
18061809
}
18071810

1808-
bool dcn32_validate_bandwidth(struct dc *dc,
1809-
struct dc_state *context,
1810-
bool fast_validate)
1811+
static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate)
18111812
{
18121813
bool out = false;
18131814

@@ -1885,6 +1886,19 @@ bool dcn32_validate_bandwidth(struct dc *dc,
18851886
return out;
18861887
}
18871888

1889+
bool dcn32_validate_bandwidth(struct dc *dc,
1890+
struct dc_state *context,
1891+
bool fast_validate)
1892+
{
1893+
bool out = false;
1894+
1895+
if (dc->debug.using_dml2)
1896+
out = dml2_validate(dc, context, fast_validate);
1897+
else
1898+
out = dml1_validate(dc, context, fast_validate);
1899+
return out;
1900+
}
1901+
18881902
int dcn32_populate_dml_pipes_from_context(
18891903
struct dc *dc, struct dc_state *context,
18901904
display_e2e_pipe_params_st *pipes,
@@ -2422,6 +2436,47 @@ static bool dcn32_resource_construct(
24222436
pool->base.oem_device = NULL;
24232437
}
24242438

2439+
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2440+
dc->dml2_options.use_native_pstate_optimization = false;
2441+
dc->dml2_options.use_native_soc_bb_construction = true;
2442+
dc->dml2_options.minimize_dispclk_using_odm = true;
2443+
2444+
dc->dml2_options.callbacks.dc = dc;
2445+
dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params;
2446+
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2447+
dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
2448+
2449+
dc->dml2_options.svp_pstate.callbacks.dc = dc;
2450+
dc->dml2_options.svp_pstate.callbacks.add_plane_to_context = &dc_add_plane_to_context;
2451+
dc->dml2_options.svp_pstate.callbacks.add_stream_to_ctx = &dc_add_stream_to_ctx;
2452+
dc->dml2_options.svp_pstate.callbacks.build_scaling_params = &resource_build_scaling_params;
2453+
dc->dml2_options.svp_pstate.callbacks.create_plane = &dc_create_plane_state;
2454+
dc->dml2_options.svp_pstate.callbacks.remove_plane_from_context = &dc_remove_plane_from_context;
2455+
dc->dml2_options.svp_pstate.callbacks.remove_stream_from_ctx = &dc_remove_stream_from_ctx;
2456+
dc->dml2_options.svp_pstate.callbacks.create_stream_for_sink = &dc_create_stream_for_sink;
2457+
dc->dml2_options.svp_pstate.callbacks.plane_state_release = &dc_plane_state_release;
2458+
dc->dml2_options.svp_pstate.callbacks.stream_release = &dc_stream_release;
2459+
dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2460+
2461+
dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2462+
dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2463+
dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2464+
dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2465+
2466+
dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2467+
dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2468+
2469+
dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2470+
dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2471+
dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2472+
dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2473+
dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2474+
dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2475+
dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2476+
2477+
dc->dml2_options.max_segments_per_hubp = 18;
2478+
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2479+
24252480
if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
24262481
dc->config.sdpif_request_limit_words_per_umc = 16;
24272482

‎drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1989,6 +1989,47 @@ static bool dcn321_resource_construct(
19891989
pool->base.oem_device = NULL;
19901990
}
19911991

1992+
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
1993+
dc->dml2_options.use_native_pstate_optimization = false;
1994+
dc->dml2_options.use_native_soc_bb_construction = true;
1995+
dc->dml2_options.minimize_dispclk_using_odm = true;
1996+
1997+
dc->dml2_options.callbacks.dc = dc;
1998+
dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params;
1999+
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2000+
dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
2001+
2002+
dc->dml2_options.svp_pstate.callbacks.dc = dc;
2003+
dc->dml2_options.svp_pstate.callbacks.add_plane_to_context = &dc_add_plane_to_context;
2004+
dc->dml2_options.svp_pstate.callbacks.add_stream_to_ctx = &dc_add_stream_to_ctx;
2005+
dc->dml2_options.svp_pstate.callbacks.build_scaling_params = &resource_build_scaling_params;
2006+
dc->dml2_options.svp_pstate.callbacks.create_plane = &dc_create_plane_state;
2007+
dc->dml2_options.svp_pstate.callbacks.remove_plane_from_context = &dc_remove_plane_from_context;
2008+
dc->dml2_options.svp_pstate.callbacks.remove_stream_from_ctx = &dc_remove_stream_from_ctx;
2009+
dc->dml2_options.svp_pstate.callbacks.create_stream_for_sink = &dc_create_stream_for_sink;
2010+
dc->dml2_options.svp_pstate.callbacks.plane_state_release = &dc_plane_state_release;
2011+
dc->dml2_options.svp_pstate.callbacks.stream_release = &dc_stream_release;
2012+
dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2013+
2014+
dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2015+
dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2016+
dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2017+
dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2018+
2019+
dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2020+
dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2021+
2022+
dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2023+
dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2024+
dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2025+
dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2026+
dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2027+
dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2028+
dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2029+
2030+
dc->dml2_options.max_segments_per_hubp = 18;
2031+
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2032+
19922033
return true;
19932034

19942035
create_fail:

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