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Casey Leedomdavem330
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PCI/cxgb4: Extend T3 PCI quirk to T4+ devices
We've run into a problem where our device is attached to a Virtual Machine and the use of the new pci_set_vpd_size() API doesn't help. The VM kernel has been informed that the accesses are okay, but all of the actual VPD Capability Accesses are trapped down into the KVM Hypervisor where it goes ahead and imposes the silent denials. The right idea is to follow the kernel.org commit 1c7de2b ("PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3)") which Alexey Kardashevskiy authored to establish a PCI Quirk for our T3-based adapters. This commit extends that PCI Quirk to cover Chelsio T4 devices and later. The advantage of this approach is that the VPD Size gets set early in the Base OS/Hypervisor Boot and doesn't require that the cxgb4 driver even be available in the Base OS/Hypervisor. Thus PF4 can be exported to a Virtual Machine and everything should work. Fixes: 67e6587 ("cxgb4: Set VPD size so we can read both VPD structures") Cc: <[email protected]> # v4.9+ Signed-off-by: Casey Leedom <[email protected]> Signed-off-by: Arjun Vynipadath <[email protected]> Signed-off-by: Ganesh Goudar <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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+23
-26
lines changed

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2637,7 +2637,6 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
26372637
}
26382638

26392639
#define EEPROM_STAT_ADDR 0x7bfc
2640-
#define VPD_SIZE 0x800
26412640
#define VPD_BASE 0x400
26422641
#define VPD_BASE_OLD 0
26432642
#define VPD_LEN 1024
@@ -2704,15 +2703,6 @@ int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
27042703
if (!vpd)
27052704
return -ENOMEM;
27062705

2707-
/* We have two VPD data structures stored in the adapter VPD area.
2708-
* By default, Linux calculates the size of the VPD area by traversing
2709-
* the first VPD area at offset 0x0, so we need to tell the OS what
2710-
* our real VPD size is.
2711-
*/
2712-
ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2713-
if (ret < 0)
2714-
goto out;
2715-
27162706
/* Card information normally starts at VPD_BASE but early cards had
27172707
* it at 0.
27182708
*/

drivers/pci/quirks.c

Lines changed: 23 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3419,22 +3419,29 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
34193419

34203420
static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
34213421
{
3422-
pci_set_vpd_size(dev, 8192);
3423-
}
3424-
3425-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
3426-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
3427-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
3428-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
3429-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
3430-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
3431-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
3432-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
3433-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
3434-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
3435-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
3436-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
3437-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
3422+
int chip = (dev->device & 0xf000) >> 12;
3423+
int func = (dev->device & 0x0f00) >> 8;
3424+
int prod = (dev->device & 0x00ff) >> 0;
3425+
3426+
/*
3427+
* If this is a T3-based adapter, there's a 1KB VPD area at offset
3428+
* 0xc00 which contains the preferred VPD values. If this is a T4 or
3429+
* later based adapter, the special VPD is at offset 0x400 for the
3430+
* Physical Functions (the SR-IOV Virtual Functions have no VPD
3431+
* Capabilities). The PCI VPD Access core routines will normally
3432+
* compute the size of the VPD by parsing the VPD Data Structure at
3433+
* offset 0x000. This will result in silent failures when attempting
3434+
* to accesses these other VPD areas which are beyond those computed
3435+
* limits.
3436+
*/
3437+
if (chip == 0x0 && prod >= 0x20)
3438+
pci_set_vpd_size(dev, 8192);
3439+
else if (chip >= 0x4 && func < 0x8)
3440+
pci_set_vpd_size(dev, 2048);
3441+
}
3442+
3443+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3444+
quirk_chelsio_extend_vpd);
34383445

34393446
#ifdef CONFIG_ACPI
34403447
/*

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