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LoongArch: Add process management
Add process management support for LoongArch, including: thread info definition, context switch and process tracing. Reviewed-by: WANG Xuerui <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/include/asm/fpu.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Author: Huacai Chen <[email protected]>
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_FPU_H
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#define _ASM_FPU_H
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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#include <linux/ptrace.h>
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#include <linux/thread_info.h>
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#include <linux/bitops.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/current.h>
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#include <asm/loongarch.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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struct sigcontext;
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extern void _init_fpu(unsigned int);
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extern void _save_fp(struct loongarch_fpu *);
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extern void _restore_fp(struct loongarch_fpu *);
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/*
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* Mask the FCSR Cause bits according to the Enable bits, observing
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* that Unimplemented is always enabled.
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*/
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static inline unsigned long mask_fcsr_x(unsigned long fcsr)
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{
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return fcsr & ((fcsr & FPU_CSR_ALL_E) <<
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(ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)));
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}
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static inline int is_fp_enabled(void)
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{
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return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPEN) ?
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1 : 0;
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}
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#define enable_fpu() set_csr_euen(CSR_EUEN_FPEN)
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#define disable_fpu() clear_csr_euen(CSR_EUEN_FPEN)
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#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
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static inline int is_fpu_owner(void)
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{
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return test_thread_flag(TIF_USEDFPU);
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}
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static inline void __own_fpu(void)
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{
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enable_fpu();
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set_thread_flag(TIF_USEDFPU);
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KSTK_EUEN(current) |= CSR_EUEN_FPEN;
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}
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static inline void own_fpu_inatomic(int restore)
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{
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if (cpu_has_fpu && !is_fpu_owner()) {
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__own_fpu();
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if (restore)
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_restore_fp(&current->thread.fpu);
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}
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}
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static inline void own_fpu(int restore)
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{
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preempt_disable();
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own_fpu_inatomic(restore);
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preempt_enable();
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}
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static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
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{
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if (is_fpu_owner()) {
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if (save)
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_save_fp(&tsk->thread.fpu);
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disable_fpu();
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clear_tsk_thread_flag(tsk, TIF_USEDFPU);
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}
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KSTK_EUEN(tsk) &= ~(CSR_EUEN_FPEN | CSR_EUEN_LSXEN | CSR_EUEN_LASXEN);
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}
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static inline void lose_fpu(int save)
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{
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preempt_disable();
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lose_fpu_inatomic(save, current);
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preempt_enable();
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}
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static inline void init_fpu(void)
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{
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unsigned int fcsr = current->thread.fpu.fcsr;
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__own_fpu();
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_init_fpu(fcsr);
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set_used_math();
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}
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static inline void save_fp(struct task_struct *tsk)
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{
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if (cpu_has_fpu)
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_save_fp(&tsk->thread.fpu);
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}
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static inline void restore_fp(struct task_struct *tsk)
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{
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if (cpu_has_fpu)
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_restore_fp(&tsk->thread.fpu);
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}
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static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
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{
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if (tsk == current) {
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preempt_disable();
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if (is_fpu_owner())
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_save_fp(&current->thread.fpu);
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preempt_enable();
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}
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return tsk->thread.fpu.fpr;
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}
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#endif /* _ASM_FPU_H */

‎arch/loongarch/include/asm/idle.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_IDLE_H
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#define __ASM_IDLE_H
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#include <linux/linkage.h>
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extern asmlinkage void __arch_cpu_idle(void);
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#endif /* __ASM_IDLE_H */

‎arch/loongarch/include/asm/mmu.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_MMU_H
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#define __ASM_MMU_H
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#include <linux/atomic.h>
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#include <linux/spinlock.h>
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typedef struct {
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u64 asid[NR_CPUS];
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void *vdso;
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} mm_context_t;
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#endif /* __ASM_MMU_H */

‎arch/loongarch/include/asm/mmu_context.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Switch a MMU context.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_MMU_CONTEXT_H
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#define _ASM_MMU_CONTEXT_H
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/mm_types.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm-generic/mm_hooks.h>
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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static inline u64 asid_version_mask(unsigned int cpu)
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{
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return ~(u64)(cpu_asid_mask(&cpu_data[cpu]));
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}
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static inline u64 asid_first_version(unsigned int cpu)
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{
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return cpu_asid_mask(&cpu_data[cpu]) + 1;
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}
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#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
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static inline int asid_valid(struct mm_struct *mm, unsigned int cpu)
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{
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if ((cpu_context(cpu, mm) ^ asid_cache(cpu)) & asid_version_mask(cpu))
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return 0;
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return 1;
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}
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/* Normal, classic get_new_mmu_context */
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static inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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{
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u64 asid = asid_cache(cpu);
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if (!((++asid) & cpu_asid_mask(&cpu_data[cpu])))
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local_flush_tlb_user(); /* start new asid cycle */
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cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for_each_possible_cpu(i)
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cpu_context(i, mm) = 0;
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return 0;
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}
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static inline void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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/* Check if our ASID is of an older version and thus invalid */
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if (!asid_valid(next, cpu))
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get_new_mmu_context(next, cpu);
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write_csr_asid(cpu_asid(cpu, next));
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if (next != &init_mm)
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csr_write64((unsigned long)next->pgd, LOONGARCH_CSR_PGDL);
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else
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csr_write64((unsigned long)invalid_pg_dir, LOONGARCH_CSR_PGDL);
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/*
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* Mark current->active_mm as not "active" anymore.
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* We don't want to mislead possible IPI tlb flush routines.
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*/
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cpumask_set_cpu(cpu, mm_cpumask(next));
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}
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#define switch_mm_irqs_off switch_mm_irqs_off
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned long flags;
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local_irq_save(flags);
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switch_mm_irqs_off(prev, next, tsk);
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local_irq_restore(flags);
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}
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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}
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#define activate_mm(prev, next) switch_mm(prev, next, current)
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#define deactivate_mm(task, mm) do { } while (0)
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/*
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* If mm is currently active, we can't really drop it.
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* Instead, we will get a new one for it.
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*/
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static inline void
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drop_mmu_context(struct mm_struct *mm, unsigned int cpu)
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{
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int asid;
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unsigned long flags;
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local_irq_save(flags);
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asid = read_csr_asid() & cpu_asid_mask(&current_cpu_data);
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if (asid == cpu_asid(cpu, mm)) {
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if (!current->mm || (current->mm == mm)) {
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get_new_mmu_context(mm, cpu);
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write_csr_asid(cpu_asid(cpu, mm));
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goto out;
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}
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}
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/* Will get a new context next time */
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cpu_context(cpu, mm) = 0;
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cpumask_clear_cpu(cpu, mm_cpumask(mm));
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out:
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local_irq_restore(flags);
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}
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#endif /* _ASM_MMU_CONTEXT_H */

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