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Merge git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
2 parents a2b8313 + 722c908 commit 80f77e5

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‎Documentation/admin-guide/kernel-parameters.txt

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1713,6 +1713,13 @@
17131713
irqaffinity= [SMP] Set the default irq affinity mask
17141714
The argument is a cpu list, as described above.
17151715

1716+
irqchip.gicv2_force_probe=
1717+
[ARM, ARM64]
1718+
Format: <bool>
1719+
Force the kernel to look for the second 4kB page
1720+
of a GICv2 controller even if the memory range
1721+
exposed by the device tree is too small.
1722+
17161723
irqfixup [HW]
17171724
When an interrupt is not handled search all handlers
17181725
for it. Intended to get systems with badly broken

‎Documentation/arm64/silicon-errata.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ stable kernels.
7070
| | | | |
7171
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
7272
| Hisilicon | Hip0{6,7} | #161010701 | N/A |
73+
| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
7374
| | | | |
7475
| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
7576
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |

‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
Amlogic meson GPIO interrupt controller
2+
3+
Meson SoCs contains an interrupt controller which is able to watch the SoC
4+
pads and generate an interrupt on edge or level. The controller is essentially
5+
a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
6+
or level and polarity. It does not expose all 256 mux inputs because the
7+
documentation shows that the upper part is not mapped to any pad. The actual
8+
number of interrupt exposed depends on the SoC.
9+
10+
Required properties:
11+
12+
- compatible : must have "amlogic,meson8-gpio-intc” and either
13+
“amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
14+
“amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
15+
“amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
16+
“amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)
17+
- interrupt-parent : a phandle to the GIC the interrupts are routed to.
18+
Usually this is provided at the root level of the device tree as it is
19+
common to most of the SoC.
20+
- reg : Specifies base physical address and size of the registers.
21+
- interrupt-controller : Identifies the node as an interrupt controller.
22+
- #interrupt-cells : Specifies the number of cells needed to encode an
23+
interrupt source. The value must be 2.
24+
- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
25+
are the hwirqs used on the parent interrupt controller.
26+
27+
Example:
28+
29+
gpio_interrupt: interrupt-controller@9880 {
30+
compatible = "amlogic,meson-gxbb-gpio-intc",
31+
"amlogic,meson-gpio-intc";
32+
reg = <0x0 0x9880 0x0 0x10>;
33+
interrupt-controller;
34+
#interrupt-cells = <2>;
35+
meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
36+
};

‎Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,10 @@ These nodes must have the following properties:
7575
- reg: Specifies the base physical address and size of the ITS
7676
registers.
7777

78+
Optional:
79+
- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
80+
address and size of the pre-ITS window.
81+
7882
The main GIC node must contain the appropriate #address-cells,
7983
#size-cells and ranges properties for the reg property of all ITS
8084
nodes.

‎Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller
22

33
Required properties:
44

5-
- compatible: should be "brcm,l2-intc"
5+
- compatible: should be "brcm,l2-intc" for latched interrupt controllers
6+
should be "brcm,bcm7271-l2-intc" for level interrupt controllers
67
- reg: specifies the base physical address and size of the registers
78
- interrupt-controller: identifies the node as an interrupt controller
89
- #interrupt-cells: specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@ Required properties:
1313
- "renesas,irqc-r8a7793" (R-Car M2-N)
1414
- "renesas,irqc-r8a7794" (R-Car E2)
1515
- "renesas,intc-ex-r8a7795" (R-Car H3)
16+
- "renesas,intc-ex-r8a7796" (R-Car M3-W)
17+
- "renesas,intc-ex-r8a77970" (R-Car V3M)
18+
- "renesas,intc-ex-r8a77995" (R-Car D3)
1619
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
1720
interrupts.txt in this directory
1821
- clocks: Must contain a reference to the functional clock.

‎arch/arm/include/asm/arch_gicv3.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,11 @@ static inline void gic_write_ctlr(u32 val)
196196
isb();
197197
}
198198

199+
static inline u32 gic_read_ctlr(void)
200+
{
201+
return read_sysreg(ICC_CTLR);
202+
}
203+
199204
static inline void gic_write_grpen1(u32 val)
200205
{
201206
write_sysreg(val, ICC_IGRPEN1);

‎arch/arm64/Kconfig

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -539,6 +539,25 @@ config QCOM_QDF2400_ERRATUM_0065
539539

540540
If unsure, say Y.
541541

542+
543+
config SOCIONEXT_SYNQUACER_PREITS
544+
bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
545+
default y
546+
help
547+
Socionext Synquacer SoCs implement a separate h/w block to generate
548+
MSI doorbell writes with non-zero values for the device ID.
549+
550+
If unsure, say Y.
551+
552+
config HISILICON_ERRATUM_161600802
553+
bool "Hip07 161600802: Erroneous redistributor VLPI base"
554+
default y
555+
help
556+
The HiSilicon Hip07 SoC usees the wrong redistributor base
557+
when issued ITS commands such as VMOVP and VMAPP, and requires
558+
a 128kB offset to be applied to the target address in this commands.
559+
560+
If unsure, say Y.
542561
endmenu
543562

544563

‎arch/arm64/include/asm/arch_gicv3.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,11 @@ static inline void gic_write_ctlr(u32 val)
8787
isb();
8888
}
8989

90+
static inline u32 gic_read_ctlr(void)
91+
{
92+
return read_sysreg_s(SYS_ICC_CTLR_EL1);
93+
}
94+
9095
static inline void gic_write_grpen1(u32 val)
9196
{
9297
write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);

‎arch/x86/include/asm/irqdomain.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,8 @@ extern int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
4141
unsigned int nr_irqs, void *arg);
4242
extern void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
4343
unsigned int nr_irqs);
44-
extern void mp_irqdomain_activate(struct irq_domain *domain,
45-
struct irq_data *irq_data);
44+
extern int mp_irqdomain_activate(struct irq_domain *domain,
45+
struct irq_data *irq_data, bool early);
4646
extern void mp_irqdomain_deactivate(struct irq_domain *domain,
4747
struct irq_data *irq_data);
4848
extern int mp_irqdomain_ioapic_idx(struct irq_domain *domain);

‎arch/x86/kernel/apic/htirq.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,8 +112,8 @@ static void htirq_domain_free(struct irq_domain *domain, unsigned int virq,
112112
irq_domain_free_irqs_top(domain, virq, nr_irqs);
113113
}
114114

115-
static void htirq_domain_activate(struct irq_domain *domain,
116-
struct irq_data *irq_data)
115+
static int htirq_domain_activate(struct irq_domain *domain,
116+
struct irq_data *irq_data, bool early)
117117
{
118118
struct ht_irq_msg msg;
119119
struct irq_cfg *cfg = irqd_cfg(irq_data);
@@ -132,6 +132,7 @@ static void htirq_domain_activate(struct irq_domain *domain,
132132
HT_IRQ_LOW_MT_ARBITRATED) |
133133
HT_IRQ_LOW_IRQ_MASKED;
134134
write_ht_irq_msg(irq_data->irq, &msg);
135+
return 0;
135136
}
136137

137138
static void htirq_domain_deactivate(struct irq_domain *domain,

‎arch/x86/kernel/apic/io_apic.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2096,7 +2096,7 @@ static inline void __init check_timer(void)
20962096
unmask_ioapic_irq(irq_get_irq_data(0));
20972097
}
20982098
irq_domain_deactivate_irq(irq_data);
2099-
irq_domain_activate_irq(irq_data);
2099+
irq_domain_activate_irq(irq_data, false);
21002100
if (timer_irq_works()) {
21012101
if (disable_timer_pin_1 > 0)
21022102
clear_IO_APIC_pin(0, pin1);
@@ -2118,7 +2118,7 @@ static inline void __init check_timer(void)
21182118
*/
21192119
replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
21202120
irq_domain_deactivate_irq(irq_data);
2121-
irq_domain_activate_irq(irq_data);
2121+
irq_domain_activate_irq(irq_data, false);
21222122
legacy_pic->unmask(0);
21232123
if (timer_irq_works()) {
21242124
apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
@@ -2977,8 +2977,8 @@ void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
29772977
irq_domain_free_irqs_top(domain, virq, nr_irqs);
29782978
}
29792979

2980-
void mp_irqdomain_activate(struct irq_domain *domain,
2981-
struct irq_data *irq_data)
2980+
int mp_irqdomain_activate(struct irq_domain *domain,
2981+
struct irq_data *irq_data, bool early)
29822982
{
29832983
unsigned long flags;
29842984
struct irq_pin_list *entry;
@@ -2988,6 +2988,7 @@ void mp_irqdomain_activate(struct irq_domain *domain,
29882988
for_each_irq_pin(entry, data->irq_2_pin)
29892989
__ioapic_write_entry(entry->apic, entry->pin, data->entry);
29902990
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2991+
return 0;
29912992
}
29922993

29932994
void mp_irqdomain_deactivate(struct irq_domain *domain,

‎arch/x86/platform/uv/uv_irq.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -127,10 +127,11 @@ static void uv_domain_free(struct irq_domain *domain, unsigned int virq,
127127
* Re-target the irq to the specified CPU and enable the specified MMR located
128128
* on the specified blade to allow the sending of MSIs to the specified CPU.
129129
*/
130-
static void uv_domain_activate(struct irq_domain *domain,
131-
struct irq_data *irq_data)
130+
static int uv_domain_activate(struct irq_domain *domain,
131+
struct irq_data *irq_data, bool early)
132132
{
133133
uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
134+
return 0;
134135
}
135136

136137
/*

‎drivers/gpio/gpio-xgene-sb.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -140,8 +140,9 @@ static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
140140
return irq_create_fwspec_mapping(&fwspec);
141141
}
142142

143-
static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
144-
struct irq_data *irq_data)
143+
static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
144+
struct irq_data *irq_data,
145+
bool early)
145146
{
146147
struct xgene_gpio_sb *priv = d->host_data;
147148
u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
@@ -150,11 +151,12 @@ static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
150151
dev_err(priv->gc.parent,
151152
"Unable to configure XGene GPIO standby pin %d as IRQ\n",
152153
gpio);
153-
return;
154+
return -ENOSPC;
154155
}
155156

156157
xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
157158
gpio * 2, 1);
159+
return 0;
158160
}
159161

160162
static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,

‎drivers/iommu/amd_iommu.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4170,8 +4170,8 @@ static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
41704170
irq_domain_free_irqs_common(domain, virq, nr_irqs);
41714171
}
41724172

4173-
static void irq_remapping_activate(struct irq_domain *domain,
4174-
struct irq_data *irq_data)
4173+
static int irq_remapping_activate(struct irq_domain *domain,
4174+
struct irq_data *irq_data, bool early)
41754175
{
41764176
struct amd_ir_data *data = irq_data->chip_data;
41774177
struct irq_2_irte *irte_info = &data->irq_2_irte;
@@ -4180,6 +4180,7 @@ static void irq_remapping_activate(struct irq_domain *domain,
41804180
if (iommu)
41814181
iommu->irte_ops->activate(data->entry, irte_info->devid,
41824182
irte_info->index);
4183+
return 0;
41834184
}
41844185

41854186
static void irq_remapping_deactivate(struct irq_domain *domain,

‎drivers/iommu/intel_irq_remapping.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1389,12 +1389,13 @@ static void intel_irq_remapping_free(struct irq_domain *domain,
13891389
irq_domain_free_irqs_common(domain, virq, nr_irqs);
13901390
}
13911391

1392-
static void intel_irq_remapping_activate(struct irq_domain *domain,
1393-
struct irq_data *irq_data)
1392+
static int intel_irq_remapping_activate(struct irq_domain *domain,
1393+
struct irq_data *irq_data, bool early)
13941394
{
13951395
struct intel_ir_data *data = irq_data->chip_data;
13961396

13971397
modify_irte(&data->irq_2_iommu, &data->irte_entry);
1398+
return 0;
13981399
}
13991400

14001401
static void intel_irq_remapping_deactivate(struct irq_domain *domain,

‎drivers/irqchip/Kconfig

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
menu "IRQ chip support"
2+
13
config IRQCHIP
24
def_bool y
35
depends on OF_IRQ
@@ -321,3 +323,13 @@ config IRQ_UNIPHIER_AIDET
321323
select IRQ_DOMAIN_HIERARCHY
322324
help
323325
Support for the UniPhier AIDET (ARM Interrupt Detector).
326+
327+
config MESON_IRQ_GPIO
328+
bool "Meson GPIO Interrupt Multiplexer"
329+
depends on ARCH_MESON
330+
select IRQ_DOMAIN
331+
select IRQ_DOMAIN_HIERARCHY
332+
help
333+
Support Meson SoC Family GPIO Interrupt Multiplexer
334+
335+
endmenu

‎drivers/irqchip/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,3 +79,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
7979
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
8080
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
8181
obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
82+
obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o

‎drivers/irqchip/irq-aspeed-i2c-ic.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,8 @@ static int __init aspeed_i2c_ic_of_init(struct device_node *node,
7676
return -ENOMEM;
7777

7878
i2c_ic->base = of_iomap(node, 0);
79-
if (IS_ERR(i2c_ic->base)) {
80-
ret = PTR_ERR(i2c_ic->base);
79+
if (!i2c_ic->base) {
80+
ret = -ENOMEM;
8181
goto err_free_ic;
8282
}
8383

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