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torvaldstorvalds
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Merge branch 'upstream-2.6.28' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-2.6.28' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: ata_piix: IDE Mode SATA patch for Intel Ibex Peak DeviceIDs libata-eh: clear UNIT ATTENTION after reset ata_piix: add Hercules EC-900 mini-notebook to ich_laptop short cable list libata: reorder ata_device to remove 8 bytes of padding on 64 bits [libata] pata_bf54x: Add proper PM operation pata_sil680: convert CONFIG_PPC_MERGE to CONFIG_PPC libata: Implement disk shock protection support [libata] Introduce ata_id_has_unload() PATA: RPC now selects HAVE_PATA_PLATFORM for pata platform driver ata_piix: drop merged SCR access and use slave_link instead libata: implement slave_link libata: misc updates to prepare for slave link libata: reimplement link iterator libata: make SCR access ops per-link
2 parents 3fa8749 + 0395e61 commit 82219fc

25 files changed

+923
-362
lines changed

‎drivers/ata/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -663,7 +663,7 @@ config HAVE_PATA_PLATFORM
663663

664664
config PATA_PLATFORM
665665
tristate "Generic platform device PATA support"
666-
depends on EMBEDDED || ARCH_RPC || PPC || HAVE_PATA_PLATFORM
666+
depends on EMBEDDED || PPC || HAVE_PATA_PLATFORM
667667
help
668668
This option enables support for generic directly connected ATA
669669
devices commonly found on embedded systems.

‎drivers/ata/ahci.c

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -267,8 +267,8 @@ struct ahci_port_priv {
267267
* per PM slot */
268268
};
269269

270-
static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
271-
static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
270+
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
271+
static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
272272
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
273273
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
274274
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
@@ -316,6 +316,7 @@ static struct device_attribute *ahci_shost_attrs[] = {
316316

317317
static struct device_attribute *ahci_sdev_attrs[] = {
318318
&dev_attr_sw_activity,
319+
&dev_attr_unload_heads,
319320
NULL
320321
};
321322

@@ -820,10 +821,10 @@ static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
820821
return 0;
821822
}
822823

823-
static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
824+
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
824825
{
825-
void __iomem *port_mmio = ahci_port_base(ap);
826-
int offset = ahci_scr_offset(ap, sc_reg);
826+
void __iomem *port_mmio = ahci_port_base(link->ap);
827+
int offset = ahci_scr_offset(link->ap, sc_reg);
827828

828829
if (offset) {
829830
*val = readl(port_mmio + offset);
@@ -832,10 +833,10 @@ static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
832833
return -EINVAL;
833834
}
834835

835-
static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
836+
static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
836837
{
837-
void __iomem *port_mmio = ahci_port_base(ap);
838-
int offset = ahci_scr_offset(ap, sc_reg);
838+
void __iomem *port_mmio = ahci_port_base(link->ap);
839+
int offset = ahci_scr_offset(link->ap, sc_reg);
839840

840841
if (offset) {
841842
writel(val, port_mmio + offset);
@@ -973,7 +974,7 @@ static void ahci_disable_alpm(struct ata_port *ap)
973974
writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
974975

975976
/* go ahead and clean out PhyRdy Change from Serror too */
976-
ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
977+
ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
977978

978979
/*
979980
* Clear flag to indicate that we should ignore all PhyRdy
@@ -1937,8 +1938,8 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
19371938
ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
19381939

19391940
/* AHCI needs SError cleared; otherwise, it might lock up */
1940-
ahci_scr_read(ap, SCR_ERROR, &serror);
1941-
ahci_scr_write(ap, SCR_ERROR, serror);
1941+
ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1942+
ahci_scr_write(&ap->link, SCR_ERROR, serror);
19421943
host_ehi->serror |= serror;
19431944

19441945
/* some controllers set IRQ_IF_ERR on device errors, ignore it */
@@ -2027,7 +2028,7 @@ static void ahci_port_intr(struct ata_port *ap)
20272028
if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
20282029
(status & PORT_IRQ_PHYRDY)) {
20292030
status &= ~PORT_IRQ_PHYRDY;
2030-
ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
2031+
ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
20312032
}
20322033

20332034
if (unlikely(status & PORT_IRQ_ERROR)) {

‎drivers/ata/ata_piix.c

Lines changed: 54 additions & 130 deletions
Original file line numberDiff line numberDiff line change
@@ -165,8 +165,10 @@ static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
165165
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166166
static int ich_pata_cable_detect(struct ata_port *ap);
167167
static u8 piix_vmw_bmdma_status(struct ata_port *ap);
168-
static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
169-
static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
168+
static int piix_sidpr_scr_read(struct ata_link *link,
169+
unsigned int reg, u32 *val);
170+
static int piix_sidpr_scr_write(struct ata_link *link,
171+
unsigned int reg, u32 val);
170172
#ifdef CONFIG_PM
171173
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
172174
static int piix_pci_device_resume(struct pci_dev *pdev);
@@ -278,12 +280,15 @@ static const struct pci_device_id piix_pci_tbl[] = {
278280
/* SATA Controller IDE (PCH) */
279281
{ 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
280282
/* SATA Controller IDE (PCH) */
283+
{ 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
284+
/* SATA Controller IDE (PCH) */
281285
{ 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
282286
/* SATA Controller IDE (PCH) */
287+
{ 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
288+
/* SATA Controller IDE (PCH) */
283289
{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
284290
/* SATA Controller IDE (PCH) */
285291
{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
286-
287292
{ } /* terminate list */
288293
};
289294

@@ -582,6 +587,7 @@ static const struct ich_laptop ich_laptop[] = {
582587
{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
583588
{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
584589
{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
590+
{ 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
585591
{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
586592
{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
587593
{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
@@ -885,144 +891,48 @@ static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
885891
* Serial ATA Index/Data Pair Superset Registers access
886892
*
887893
* Beginning from ICH8, there's a sane way to access SCRs using index
888-
* and data register pair located at BAR5. This creates an
889-
* interesting problem of mapping two SCRs to one port.
890-
*
891-
* Although they have separate SCRs, the master and slave aren't
892-
* independent enough to be treated as separate links - e.g. softreset
893-
* resets both. Also, there's no protocol defined for hard resetting
894-
* singled device sharing the virtual port (no defined way to acquire
895-
* device signature). This is worked around by merging the SCR values
896-
* into one sensible value and requesting follow-up SRST after
897-
* hardreset.
898-
*
899-
* SCR merging is perfomed in nibbles which is the unit contents in
900-
* SCRs are organized. If two values are equal, the value is used.
901-
* When they differ, merge table which lists precedence of possible
902-
* values is consulted and the first match or the last entry when
903-
* nothing matches is used. When there's no merge table for the
904-
* specific nibble, value from the first port is used.
894+
* and data register pair located at BAR5 which means that we have
895+
* separate SCRs for master and slave. This is handled using libata
896+
* slave_link facility.
905897
*/
906898
static const int piix_sidx_map[] = {
907899
[SCR_STATUS] = 0,
908900
[SCR_ERROR] = 2,
909901
[SCR_CONTROL] = 1,
910902
};
911903

912-
static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
904+
static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
913905
{
914-
struct ata_port *ap = dev->link->ap;
906+
struct ata_port *ap = link->ap;
915907
struct piix_host_priv *hpriv = ap->host->private_data;
916908

917-
iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
909+
iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
918910
hpriv->sidpr + PIIX_SIDPR_IDX);
919911
}
920912

921-
static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
922-
{
923-
struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
924-
925-
piix_sidpr_sel(dev, reg);
926-
return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
927-
}
928-
929-
static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
930-
{
931-
struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
932-
933-
piix_sidpr_sel(dev, reg);
934-
iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
935-
}
936-
937-
static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
938-
{
939-
u32 val = 0;
940-
int i, mi;
941-
942-
for (i = 0, mi = 0; i < 32 / 4; i++) {
943-
u8 c0 = (val0 >> (i * 4)) & 0xf;
944-
u8 c1 = (val1 >> (i * 4)) & 0xf;
945-
u8 merged = c0;
946-
const int *cur;
947-
948-
/* if no merge preference, assume the first value */
949-
cur = merge_tbl[mi];
950-
if (!cur)
951-
goto done;
952-
mi++;
953-
954-
/* if two values equal, use it */
955-
if (c0 == c1)
956-
goto done;
957-
958-
/* choose the first match or the last from the merge table */
959-
while (*cur != -1) {
960-
if (c0 == *cur || c1 == *cur)
961-
break;
962-
cur++;
963-
}
964-
if (*cur == -1)
965-
cur--;
966-
merged = *cur;
967-
done:
968-
val |= merged << (i * 4);
969-
}
970-
971-
return val;
972-
}
973-
974-
static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
913+
static int piix_sidpr_scr_read(struct ata_link *link,
914+
unsigned int reg, u32 *val)
975915
{
976-
const int * const sstatus_merge_tbl[] = {
977-
/* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
978-
/* SPD */ (const int []){ 2, 1, 0, -1 },
979-
/* IPM */ (const int []){ 6, 2, 1, 0, -1 },
980-
NULL,
981-
};
982-
const int * const scontrol_merge_tbl[] = {
983-
/* DET */ (const int []){ 1, 0, 4, 0, -1 },
984-
/* SPD */ (const int []){ 0, 2, 1, 0, -1 },
985-
/* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
986-
NULL,
987-
};
988-
u32 v0, v1;
916+
struct piix_host_priv *hpriv = link->ap->host->private_data;
989917

990918
if (reg >= ARRAY_SIZE(piix_sidx_map))
991919
return -EINVAL;
992920

993-
if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
994-
*val = piix_sidpr_read(&ap->link.device[0], reg);
995-
return 0;
996-
}
997-
998-
v0 = piix_sidpr_read(&ap->link.device[0], reg);
999-
v1 = piix_sidpr_read(&ap->link.device[1], reg);
1000-
1001-
switch (reg) {
1002-
case SCR_STATUS:
1003-
*val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
1004-
break;
1005-
case SCR_ERROR:
1006-
*val = v0 | v1;
1007-
break;
1008-
case SCR_CONTROL:
1009-
*val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1010-
break;
1011-
}
1012-
921+
piix_sidpr_sel(link, reg);
922+
*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1013923
return 0;
1014924
}
1015925

1016-
static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
926+
static int piix_sidpr_scr_write(struct ata_link *link,
927+
unsigned int reg, u32 val)
1017928
{
929+
struct piix_host_priv *hpriv = link->ap->host->private_data;
930+
1018931
if (reg >= ARRAY_SIZE(piix_sidx_map))
1019932
return -EINVAL;
1020933

1021-
piix_sidpr_write(&ap->link.device[0], reg, val);
1022-
1023-
if (ap->flags & ATA_FLAG_SLAVE_POSS)
1024-
piix_sidpr_write(&ap->link.device[1], reg, val);
1025-
934+
piix_sidpr_sel(link, reg);
935+
iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1026936
return 0;
1027937
}
1028938

@@ -1363,55 +1273,67 @@ static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
13631273
return map;
13641274
}
13651275

1366-
static void __devinit piix_init_sidpr(struct ata_host *host)
1276+
static int __devinit piix_init_sidpr(struct ata_host *host)
13671277
{
13681278
struct pci_dev *pdev = to_pci_dev(host->dev);
13691279
struct piix_host_priv *hpriv = host->private_data;
1370-
struct ata_device *dev0 = &host->ports[0]->link.device[0];
1280+
struct ata_link *link0 = &host->ports[0]->link;
13711281
u32 scontrol;
1372-
int i;
1282+
int i, rc;
13731283

13741284
/* check for availability */
13751285
for (i = 0; i < 4; i++)
13761286
if (hpriv->map[i] == IDE)
1377-
return;
1287+
return 0;
13781288

13791289
if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1380-
return;
1290+
return 0;
13811291

13821292
if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
13831293
pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1384-
return;
1294+
return 0;
13851295

13861296
if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1387-
return;
1297+
return 0;
13881298

13891299
hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
13901300

13911301
/* SCR access via SIDPR doesn't work on some configurations.
13921302
* Give it a test drive by inhibiting power save modes which
13931303
* we'll do anyway.
13941304
*/
1395-
scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1305+
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
13961306

13971307
/* if IPM is already 3, SCR access is probably working. Don't
13981308
* un-inhibit power save modes as BIOS might have inhibited
13991309
* them for a reason.
14001310
*/
14011311
if ((scontrol & 0xf00) != 0x300) {
14021312
scontrol |= 0x300;
1403-
piix_sidpr_write(dev0, SCR_CONTROL, scontrol);
1404-
scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1313+
piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1314+
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
14051315

14061316
if ((scontrol & 0xf00) != 0x300) {
14071317
dev_printk(KERN_INFO, host->dev, "SCR access via "
14081318
"SIDPR is available but doesn't work\n");
1409-
return;
1319+
return 0;
14101320
}
14111321
}
14121322

1413-
host->ports[0]->ops = &piix_sidpr_sata_ops;
1414-
host->ports[1]->ops = &piix_sidpr_sata_ops;
1323+
/* okay, SCRs available, set ops and ask libata for slave_link */
1324+
for (i = 0; i < 2; i++) {
1325+
struct ata_port *ap = host->ports[i];
1326+
1327+
ap->ops = &piix_sidpr_sata_ops;
1328+
1329+
if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1330+
rc = ata_slave_link_init(ap);
1331+
if (rc)
1332+
return rc;
1333+
}
1334+
}
1335+
1336+
return 0;
14151337
}
14161338

14171339
static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
@@ -1521,7 +1443,9 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
15211443
/* initialize controller */
15221444
if (port_flags & ATA_FLAG_SATA) {
15231445
piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1524-
piix_init_sidpr(host);
1446+
rc = piix_init_sidpr(host);
1447+
if (rc)
1448+
return rc;
15251449
}
15261450

15271451
/* apply IOCFG bit18 quirk */

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