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LorenzoBianconibebarino
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clk: en7523: move en7581_reset_register() in en7581_clk_hw_init()
Move en7581_reset_register routine in en7581_clk_hw_init() since reset feature is supported just by EN7581 SoC. Get rid of reset struct in en_clk_soc_data data struct. Signed-off-by: Lorenzo Bianconi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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drivers/clk/clk-en7523.c

Lines changed: 33 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -76,11 +76,6 @@ struct en_rst_data {
7676

7777
struct en_clk_soc_data {
7878
const struct clk_ops pcie_ops;
79-
struct {
80-
const u16 *bank_ofs;
81-
const u16 *idx_map;
82-
u16 idx_map_nr;
83-
} reset;
8479
int (*hw_init)(struct platform_device *pdev,
8580
struct clk_hw_onecell_data *clk_data);
8681
};
@@ -595,32 +590,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat
595590
clk_data->num = EN7523_NUM_CLOCKS;
596591
}
597592

598-
static int en7581_clk_hw_init(struct platform_device *pdev,
599-
struct clk_hw_onecell_data *clk_data)
600-
{
601-
void __iomem *np_base;
602-
struct regmap *map;
603-
u32 val;
604-
605-
map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
606-
if (IS_ERR(map))
607-
return PTR_ERR(map);
608-
609-
np_base = devm_platform_ioremap_resource(pdev, 0);
610-
if (IS_ERR(np_base))
611-
return PTR_ERR(np_base);
612-
613-
en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
614-
615-
val = readl(np_base + REG_NP_SCU_SSTR);
616-
val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
617-
writel(val, np_base + REG_NP_SCU_SSTR);
618-
val = readl(np_base + REG_NP_SCU_PCIC);
619-
writel(val | 3, np_base + REG_NP_SCU_PCIC);
620-
621-
return 0;
622-
}
623-
624593
static int en7523_reset_update(struct reset_controller_dev *rcdev,
625594
unsigned long id, bool assert)
626595
{
@@ -670,23 +639,18 @@ static int en7523_reset_xlate(struct reset_controller_dev *rcdev,
670639
return rst_data->idx_map[reset_spec->args[0]];
671640
}
672641

673-
static const struct reset_control_ops en7523_reset_ops = {
642+
static const struct reset_control_ops en7581_reset_ops = {
674643
.assert = en7523_reset_assert,
675644
.deassert = en7523_reset_deassert,
676645
.status = en7523_reset_status,
677646
};
678647

679-
static int en7523_reset_register(struct platform_device *pdev,
680-
const struct en_clk_soc_data *soc_data)
648+
static int en7581_reset_register(struct platform_device *pdev)
681649
{
682650
struct device *dev = &pdev->dev;
683651
struct en_rst_data *rst_data;
684652
void __iomem *base;
685653

686-
/* no reset lines available */
687-
if (!soc_data->reset.idx_map_nr)
688-
return 0;
689-
690654
base = devm_platform_ioremap_resource(pdev, 1);
691655
if (IS_ERR(base))
692656
return PTR_ERR(base);
@@ -695,13 +659,13 @@ static int en7523_reset_register(struct platform_device *pdev,
695659
if (!rst_data)
696660
return -ENOMEM;
697661

698-
rst_data->bank_ofs = soc_data->reset.bank_ofs;
699-
rst_data->idx_map = soc_data->reset.idx_map;
662+
rst_data->bank_ofs = en7581_rst_ofs;
663+
rst_data->idx_map = en7581_rst_map;
700664
rst_data->base = base;
701665

702-
rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
666+
rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map);
703667
rst_data->rcdev.of_xlate = en7523_reset_xlate;
704-
rst_data->rcdev.ops = &en7523_reset_ops;
668+
rst_data->rcdev.ops = &en7581_reset_ops;
705669
rst_data->rcdev.of_node = dev->of_node;
706670
rst_data->rcdev.of_reset_n_cells = 1;
707671
rst_data->rcdev.owner = THIS_MODULE;
@@ -710,6 +674,32 @@ static int en7523_reset_register(struct platform_device *pdev,
710674
return devm_reset_controller_register(dev, &rst_data->rcdev);
711675
}
712676

677+
static int en7581_clk_hw_init(struct platform_device *pdev,
678+
struct clk_hw_onecell_data *clk_data)
679+
{
680+
void __iomem *np_base;
681+
struct regmap *map;
682+
u32 val;
683+
684+
map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
685+
if (IS_ERR(map))
686+
return PTR_ERR(map);
687+
688+
np_base = devm_platform_ioremap_resource(pdev, 0);
689+
if (IS_ERR(np_base))
690+
return PTR_ERR(np_base);
691+
692+
en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
693+
694+
val = readl(np_base + REG_NP_SCU_SSTR);
695+
val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
696+
writel(val, np_base + REG_NP_SCU_SSTR);
697+
val = readl(np_base + REG_NP_SCU_PCIC);
698+
writel(val | 3, np_base + REG_NP_SCU_PCIC);
699+
700+
return en7581_reset_register(pdev);
701+
}
702+
713703
static int en7523_clk_probe(struct platform_device *pdev)
714704
{
715705
struct device_node *node = pdev->dev.of_node;
@@ -728,19 +718,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
728718
if (r)
729719
return r;
730720

731-
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
732-
if (r)
733-
return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
734-
pdev->name);
735-
736-
r = en7523_reset_register(pdev, soc_data);
737-
if (r) {
738-
of_clk_del_provider(node);
739-
return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
740-
pdev->name);
741-
}
742-
743-
return 0;
721+
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
744722
}
745723

746724
static const struct en_clk_soc_data en7523_data = {
@@ -758,11 +736,6 @@ static const struct en_clk_soc_data en7581_data = {
758736
.enable = en7581_pci_enable,
759737
.disable = en7581_pci_disable,
760738
},
761-
.reset = {
762-
.bank_ofs = en7581_rst_ofs,
763-
.idx_map = en7581_rst_map,
764-
.idx_map_nr = ARRAY_SIZE(en7581_rst_map),
765-
},
766739
.hw_init = en7581_clk_hw_init,
767740
};
768741

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