Skip to content

Commit 89d62bc

Browse files
author
Kalle Valo
committed
Merge tag 'ath-next-20250114' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
ath.git patches for v6.14 This development cycle again featured multiple patchsets to ath12k to support the new 802.11be MLO feature, this time including the device grouping infrastructure, and the advertisement of MLO support to the wireless core. However the MLO feature is still considered to be incomplete. In addition, there was the usual set of bug fixes and cleanups, mostly in ath12k, but also in ath9k.
2 parents 208dea9 + 336097d commit 89d62bc

File tree

33 files changed

+2723
-547
lines changed

33 files changed

+2723
-547
lines changed

‎Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml

Lines changed: 204 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,204 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/net/wireless/qcom,ath12k-wsi.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Qualcomm Technologies ath12k wireless devices (PCIe) with WSI interface
9+
10+
maintainers:
11+
- Jeff Johnson <[email protected]>
12+
- Kalle Valo <[email protected]>
13+
14+
description: |
15+
Qualcomm Technologies IEEE 802.11be PCIe devices with WSI interface.
16+
17+
The ath12k devices (QCN9274) feature WSI support. WSI stands for
18+
WLAN Serial Interface. It is used for the exchange of specific
19+
control information across radios based on the doorbell mechanism.
20+
This WSI connection is essential to exchange control information
21+
among these devices.
22+
23+
The WSI interface includes TX and RX ports, which are used to connect
24+
multiple WSI-supported devices together, forming a WSI group.
25+
26+
Diagram to represent one WSI connection (one WSI group) among
27+
three devices.
28+
29+
+-------+ +-------+ +-------+
30+
| pcie1 | | pcie2 | | pcie3 |
31+
| | | | | |
32+
+----->| wsi |------->| wsi |------->| wsi |-----+
33+
| | grp 0 | | grp 0 | | grp 0 | |
34+
| +-------+ +-------+ +-------+ |
35+
+------------------------------------------------------+
36+
37+
Diagram to represent two WSI connections (two separate WSI groups)
38+
among four devices.
39+
40+
+-------+ +-------+ +-------+ +-------+
41+
| pcie0 | | pcie1 | | pcie2 | | pcie3 |
42+
| | | | | | | |
43+
+-->| wsi |--->| wsi |--+ +-->| wsi |--->| wsi |--+
44+
| | grp 0 | | grp 0 | | | | grp 1 | | grp 1 | |
45+
| +-------+ +-------+ | | +-------+ +-------+ |
46+
+---------------------------+ +---------------------------+
47+
48+
properties:
49+
compatible:
50+
enum:
51+
- pci17cb,1109 # QCN9274
52+
53+
reg:
54+
maxItems: 1
55+
56+
qcom,ath12k-calibration-variant:
57+
$ref: /schemas/types.yaml#/definitions/string
58+
description:
59+
String to uniquely identify variant of the calibration data for designs
60+
with colliding bus and device ids
61+
62+
qcom,wsi-controller:
63+
$ref: /schemas/types.yaml#/definitions/flag
64+
description:
65+
The WSI controller device in the WSI group aids (is capable) to
66+
synchronize the Timing Synchronization Function (TSF) clock across
67+
all devices in the WSI group.
68+
69+
ports:
70+
$ref: /schemas/graph.yaml#/properties/ports
71+
properties:
72+
port@0:
73+
$ref: /schemas/graph.yaml#/properties/port
74+
description:
75+
This is the TX port of WSI interface. It is attached to the RX
76+
port of the next device in the WSI connection.
77+
78+
port@1:
79+
$ref: /schemas/graph.yaml#/properties/port
80+
description:
81+
This is the RX port of WSI interface. It is attached to the TX
82+
port of the previous device in the WSI connection.
83+
84+
required:
85+
- compatible
86+
- reg
87+
88+
additionalProperties: false
89+
90+
examples:
91+
- |
92+
pcie {
93+
#address-cells = <3>;
94+
#size-cells = <2>;
95+
96+
pcie@0 {
97+
device_type = "pci";
98+
reg = <0x0 0x0 0x0 0x0 0x0>;
99+
#address-cells = <3>;
100+
#size-cells = <2>;
101+
ranges;
102+
103+
wifi@0 {
104+
compatible = "pci17cb,1109";
105+
reg = <0x0 0x0 0x0 0x0 0x0>;
106+
107+
qcom,ath12k-calibration-variant = "RDP433_1";
108+
109+
ports {
110+
#address-cells = <1>;
111+
#size-cells = <0>;
112+
113+
port@0 {
114+
reg = <0>;
115+
116+
wifi1_wsi_tx: endpoint {
117+
remote-endpoint = <&wifi2_wsi_rx>;
118+
};
119+
};
120+
121+
port@1 {
122+
reg = <1>;
123+
124+
wifi1_wsi_rx: endpoint {
125+
remote-endpoint = <&wifi3_wsi_tx>;
126+
};
127+
};
128+
};
129+
};
130+
};
131+
132+
pcie@1 {
133+
device_type = "pci";
134+
reg = <0x0 0x0 0x1 0x0 0x0>;
135+
#address-cells = <3>;
136+
#size-cells = <2>;
137+
ranges;
138+
139+
wifi@0 {
140+
compatible = "pci17cb,1109";
141+
reg = <0x0 0x0 0x0 0x0 0x0>;
142+
143+
qcom,ath12k-calibration-variant = "RDP433_2";
144+
qcom,wsi-controller;
145+
146+
ports {
147+
#address-cells = <1>;
148+
#size-cells = <0>;
149+
150+
port@0 {
151+
reg = <0>;
152+
153+
wifi2_wsi_tx: endpoint {
154+
remote-endpoint = <&wifi3_wsi_rx>;
155+
};
156+
};
157+
158+
port@1 {
159+
reg = <1>;
160+
161+
wifi2_wsi_rx: endpoint {
162+
remote-endpoint = <&wifi1_wsi_tx>;
163+
};
164+
};
165+
};
166+
};
167+
};
168+
169+
pcie@2 {
170+
device_type = "pci";
171+
reg = <0x0 0x0 0x2 0x0 0x0>;
172+
#address-cells = <3>;
173+
#size-cells = <2>;
174+
ranges;
175+
176+
wifi@0 {
177+
compatible = "pci17cb,1109";
178+
reg = <0x0 0x0 0x0 0x0 0x0>;
179+
180+
qcom,ath12k-calibration-variant = "RDP433_3";
181+
182+
ports {
183+
#address-cells = <1>;
184+
#size-cells = <0>;
185+
186+
port@0 {
187+
reg = <0>;
188+
189+
wifi3_wsi_tx: endpoint {
190+
remote-endpoint = <&wifi1_wsi_rx>;
191+
};
192+
};
193+
194+
port@1 {
195+
reg = <1>;
196+
197+
wifi3_wsi_rx: endpoint {
198+
remote-endpoint = <&wifi2_wsi_tx>;
199+
};
200+
};
201+
};
202+
};
203+
};
204+
};

0 commit comments

Comments
 (0)