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net: dsa: Introduce driver for NXP SJA1105 5-port L2 switch
At this moment the following is supported: * Link state management through phylib * Autonomous L2 forwarding managed through iproute2 bridge commands. IP termination must be done currently through the master netdevice, since the switch is unmanaged at this point and using DSA_TAG_PROTO_NONE. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: Georg Waibel <[email protected]> Acked-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎MAINTAINERS

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F: Documentation/devicetree/bindings/sound/sgtl5000.txt
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F: sound/soc/codecs/sgtl5000*
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NXP SJA1105 ETHERNET SWITCH DRIVER
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M: Vladimir Oltean <[email protected]>
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L: [email protected]
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S: Maintained
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F: drivers/net/dsa/sja1105
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NXP TDA998X DRM DRIVER
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M: Russell King <[email protected]>
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S: Maintained

‎drivers/net/dsa/Kconfig

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@@ -51,6 +51,8 @@ source "drivers/net/dsa/microchip/Kconfig"
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source "drivers/net/dsa/mv88e6xxx/Kconfig"
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source "drivers/net/dsa/sja1105/Kconfig"
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config NET_DSA_QCA8K
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tristate "Qualcomm Atheros QCA8K Ethernet switch family support"
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depends on NET_DSA

‎drivers/net/dsa/Makefile

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@@ -18,3 +18,4 @@ obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) += vitesse-vsc73xx.o
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obj-y += b53/
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obj-y += microchip/
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obj-y += mv88e6xxx/
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obj-y += sja1105/

‎drivers/net/dsa/sja1105/Kconfig

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config NET_DSA_SJA1105
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tristate "NXP SJA1105 Ethernet switch family support"
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depends on NET_DSA && SPI
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select PACKING
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select CRC32
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help
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This is the driver for the NXP SJA1105 automotive Ethernet switch
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family. These are 5-port devices and are managed over an SPI
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interface. Probing is handled based on OF bindings and so is the
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linkage to phylib. The driver supports the following revisions:
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- SJA1105E (Gen. 1, No TT-Ethernet)
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- SJA1105T (Gen. 1, TT-Ethernet)
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- SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
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- SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
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- SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
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- SJA1105S (Gen. 2, SGMII, TT-Ethernet)

‎drivers/net/dsa/sja1105/Makefile

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obj-$(CONFIG_NET_DSA_SJA1105) += sja1105.o
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sja1105-objs := \
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sja1105_spi.o \
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sja1105_main.o \
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sja1105_clocking.o \
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sja1105_static_config.o \
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sja1105_dynamic_config.o \

‎drivers/net/dsa/sja1105/sja1105.h

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/* SPDX-License-Identifier: GPL-2.0
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* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
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* Copyright (c) 2018-2019, Vladimir Oltean <[email protected]>
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*/
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#ifndef _SJA1105_H
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#define _SJA1105_H
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#include <linux/dsa/sja1105.h>
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#include <net/dsa.h>
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#include "sja1105_static_config.h"
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#define SJA1105_NUM_PORTS 5
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#define SJA1105_NUM_TC 8
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#define SJA1105ET_FDB_BIN_SIZE 4
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/* Keeps the different addresses between E/T and P/Q/R/S */
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struct sja1105_regs {
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u64 device_id;
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u64 prod_id;
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u64 status;
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u64 rgu;
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u64 config;
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u64 rmii_pll1;
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u64 pad_mii_tx[SJA1105_NUM_PORTS];
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u64 cgu_idiv[SJA1105_NUM_PORTS];
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u64 rgmii_pad_mii_tx[SJA1105_NUM_PORTS];
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u64 mii_tx_clk[SJA1105_NUM_PORTS];
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u64 mii_rx_clk[SJA1105_NUM_PORTS];
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u64 mii_ext_tx_clk[SJA1105_NUM_PORTS];
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u64 mii_ext_rx_clk[SJA1105_NUM_PORTS];
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u64 rgmii_tx_clk[SJA1105_NUM_PORTS];
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u64 rmii_ref_clk[SJA1105_NUM_PORTS];
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u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS];
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u64 mac[SJA1105_NUM_PORTS];
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u64 mac_hl1[SJA1105_NUM_PORTS];
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u64 mac_hl2[SJA1105_NUM_PORTS];
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u64 qlevel[SJA1105_NUM_PORTS];
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};
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struct sja1105_info {
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u64 device_id;
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/* Needed for distinction between P and R, and between Q and S
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* (since the parts with/without SGMII share the same
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* switch core and device_id)
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*/
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u64 part_no;
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const struct sja1105_dynamic_table_ops *dyn_ops;
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const struct sja1105_table_ops *static_ops;
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const struct sja1105_regs *regs;
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int (*reset_cmd)(const void *ctx, const void *data);
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const char *name;
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};
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struct sja1105_private {
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struct sja1105_static_config static_config;
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const struct sja1105_info *info;
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struct gpio_desc *reset_gpio;
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struct spi_device *spidev;
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struct dsa_switch *ds;
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};
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#include "sja1105_dynamic_config.h"
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struct sja1105_spi_message {
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u64 access;
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u64 read_count;
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u64 address;
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};
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typedef enum {
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SPI_READ = 0,
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SPI_WRITE = 1,
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} sja1105_spi_rw_mode_t;
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/* From sja1105_spi.c */
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int sja1105_spi_send_packed_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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void *packed_buf, size_t size_bytes);
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int sja1105_spi_send_int(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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u64 *value, u64 size_bytes);
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int sja1105_spi_send_long_packed_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 base_addr,
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void *packed_buf, u64 buf_len);
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int sja1105_static_config_upload(struct sja1105_private *priv);
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extern struct sja1105_info sja1105e_info;
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extern struct sja1105_info sja1105t_info;
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extern struct sja1105_info sja1105p_info;
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extern struct sja1105_info sja1105q_info;
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extern struct sja1105_info sja1105r_info;
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extern struct sja1105_info sja1105s_info;
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/* From sja1105_clocking.c */
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typedef enum {
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XMII_MAC = 0,
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XMII_PHY = 1,
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} sja1105_mii_role_t;
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typedef enum {
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XMII_MODE_MII = 0,
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XMII_MODE_RMII = 1,
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XMII_MODE_RGMII = 2,
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} sja1105_phy_interface_t;
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typedef enum {
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SJA1105_SPEED_10MBPS = 3,
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SJA1105_SPEED_100MBPS = 2,
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SJA1105_SPEED_1000MBPS = 1,
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SJA1105_SPEED_AUTO = 0,
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} sja1105_speed_t;
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int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
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int sja1105_clocking_setup(struct sja1105_private *priv);
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/* From sja1105_dynamic_config.c */
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int sja1105_dynamic_config_read(struct sja1105_private *priv,
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enum sja1105_blk_idx blk_idx,
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int index, void *entry);
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int sja1105_dynamic_config_write(struct sja1105_private *priv,
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enum sja1105_blk_idx blk_idx,
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int index, void *entry, bool keep);
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/* Common implementations for the static and dynamic configs */
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size_t sja1105_l2_forwarding_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105pqrs_l2_lookup_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105et_l2_lookup_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105_vlan_lookup_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105pqrs_mac_config_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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#endif

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