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Merge tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller changes for v5.3 This tag adds support for the Bitmain BM1880 reset controller to the reset-simple driver and fixes a spelling mistake in the i.MX7 reset controller binding document. * tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux: dt-bindings: reset: imx7: Fix the spelling of 'indices' reset: Add reset controller support for BM1880 SoC dt-bindings: reset: Add devicetree binding for BM1880 reset controller Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
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Bitmain BM1880 SoC Reset Controller
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===================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "bitmain,bm1880-reset"
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- reg: Offset and length of reset controller space in SCTRL.
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- #reset-cells: Must be 1.
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Example:
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rst: reset-controller@c00 {
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compatible = "bitmain,bm1880-reset";
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reg = <0xc00 0x8>;
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#reset-cells = <1>;
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};

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

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};
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48-
For list of all valid reset indicies see
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For list of all valid reset indices see
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<dt-bindings/reset/imx7-reset.h> for i.MX7 and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ

drivers/reset/Kconfig

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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST
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default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
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default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN
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help
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This enables a simple reset controller driver for reset lines that
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that can be asserted and deasserted by toggling bits in a contiguous,
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- RCC reset controller in STM32 MCUs
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- Allwinner SoCs
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- ZTE's zx2967 family
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- Bitmain BM1880 SoC
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config RESET_STM32MP157
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bool "STM32MP157 Reset Driver" if COMPILE_TEST

drivers/reset/reset-simple.c

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.data = &reset_simple_active_low },
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{ .compatible = "aspeed,ast2400-lpc-reset" },
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{ .compatible = "aspeed,ast2500-lpc-reset" },
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{ .compatible = "bitmain,bm1880-reset",
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.data = &reset_simple_active_low },
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{ /* sentinel */ },
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};
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2018 Bitmain Ltd.
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* Copyright (c) 2019 Linaro Ltd.
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*/
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#ifndef _DT_BINDINGS_BM1880_RESET_H
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#define _DT_BINDINGS_BM1880_RESET_H
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#define BM1880_RST_MAIN_AP 0
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#define BM1880_RST_SECOND_AP 1
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#define BM1880_RST_DDR 2
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#define BM1880_RST_VIDEO 3
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#define BM1880_RST_JPEG 4
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#define BM1880_RST_VPP 5
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#define BM1880_RST_GDMA 6
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#define BM1880_RST_AXI_SRAM 7
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#define BM1880_RST_TPU 8
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#define BM1880_RST_USB 9
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#define BM1880_RST_ETH0 10
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#define BM1880_RST_ETH1 11
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#define BM1880_RST_NAND 12
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#define BM1880_RST_EMMC 13
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#define BM1880_RST_SD 14
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#define BM1880_RST_SDMA 15
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#define BM1880_RST_I2S0 16
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#define BM1880_RST_I2S1 17
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#define BM1880_RST_UART0_1_CLK 18
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#define BM1880_RST_UART0_1_ACLK 19
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#define BM1880_RST_UART2_3_CLK 20
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#define BM1880_RST_UART2_3_ACLK 21
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#define BM1880_RST_MINER 22
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#define BM1880_RST_I2C0 23
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#define BM1880_RST_I2C1 24
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#define BM1880_RST_I2C2 25
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#define BM1880_RST_I2C3 26
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#define BM1880_RST_I2C4 27
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#define BM1880_RST_PWM0 28
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#define BM1880_RST_PWM1 29
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#define BM1880_RST_PWM2 30
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#define BM1880_RST_PWM3 31
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#define BM1880_RST_SPI 32
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#define BM1880_RST_GPIO0 33
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#define BM1880_RST_GPIO1 34
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#define BM1880_RST_GPIO2 35
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#define BM1880_RST_EFUSE 36
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#define BM1880_RST_WDT 37
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#define BM1880_RST_AHB_ROM 38
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#define BM1880_RST_SPIC 39
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#endif /* _DT_BINDINGS_BM1880_RESET_H */

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