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1 | 1 | // SPDX-License-Identifier: GPL-2.0
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2 |
| -/* Copyright(c) 2013 - 2018 Intel Corporation. */ |
| 2 | +/* Copyright(c) 2013 - 2021 Intel Corporation. */ |
3 | 3 |
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4 | 4 | #include "i40e.h"
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5 | 5 | #include "i40e_type.h"
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@@ -3661,6 +3661,46 @@ i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
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3661 | 3661 | return status;
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3662 | 3662 | }
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3663 | 3663 |
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| 3664 | +/** |
| 3665 | + * i40e_aq_set_lldp_mib - Set the LLDP MIB |
| 3666 | + * @hw: pointer to the hw struct |
| 3667 | + * @mib_type: Local, Remote or both Local and Remote MIBs |
| 3668 | + * @buff: pointer to a user supplied buffer to store the MIB block |
| 3669 | + * @buff_size: size of the buffer (in bytes) |
| 3670 | + * @cmd_details: pointer to command details structure or NULL |
| 3671 | + * |
| 3672 | + * Set the LLDP MIB. |
| 3673 | + **/ |
| 3674 | +enum i40e_status_code |
| 3675 | +i40e_aq_set_lldp_mib(struct i40e_hw *hw, |
| 3676 | + u8 mib_type, void *buff, u16 buff_size, |
| 3677 | + struct i40e_asq_cmd_details *cmd_details) |
| 3678 | +{ |
| 3679 | + struct i40e_aqc_lldp_set_local_mib *cmd; |
| 3680 | + enum i40e_status_code status; |
| 3681 | + struct i40e_aq_desc desc; |
| 3682 | + |
| 3683 | + cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; |
| 3684 | + if (buff_size == 0 || !buff) |
| 3685 | + return I40E_ERR_PARAM; |
| 3686 | + |
| 3687 | + i40e_fill_default_direct_cmd_desc(&desc, |
| 3688 | + i40e_aqc_opc_lldp_set_local_mib); |
| 3689 | + /* Indirect Command */ |
| 3690 | + desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); |
| 3691 | + if (buff_size > I40E_AQ_LARGE_BUF) |
| 3692 | + desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); |
| 3693 | + desc.datalen = cpu_to_le16(buff_size); |
| 3694 | + |
| 3695 | + cmd->type = mib_type; |
| 3696 | + cmd->length = cpu_to_le16(buff_size); |
| 3697 | + cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); |
| 3698 | + cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); |
| 3699 | + |
| 3700 | + status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); |
| 3701 | + return status; |
| 3702 | +} |
| 3703 | + |
3664 | 3704 | /**
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3665 | 3705 | * i40e_aq_cfg_lldp_mib_change_event
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3666 | 3706 | * @hw: pointer to the hw struct
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@@ -4479,6 +4519,29 @@ static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
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4479 | 4519 | return status;
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4480 | 4520 | }
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4481 | 4521 |
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| 4522 | +/** |
| 4523 | + * i40e_aq_suspend_port_tx |
| 4524 | + * @hw: pointer to the hardware structure |
| 4525 | + * @seid: port seid |
| 4526 | + * @cmd_details: pointer to command details structure or NULL |
| 4527 | + * |
| 4528 | + * Suspend port's Tx traffic |
| 4529 | + **/ |
| 4530 | +i40e_status i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, |
| 4531 | + struct i40e_asq_cmd_details *cmd_details) |
| 4532 | +{ |
| 4533 | + struct i40e_aqc_tx_sched_ind *cmd; |
| 4534 | + struct i40e_aq_desc desc; |
| 4535 | + i40e_status status; |
| 4536 | + |
| 4537 | + cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; |
| 4538 | + i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); |
| 4539 | + cmd->vsi_seid = cpu_to_le16(seid); |
| 4540 | + status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); |
| 4541 | + |
| 4542 | + return status; |
| 4543 | +} |
| 4544 | + |
4482 | 4545 | /**
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4483 | 4546 | * i40e_aq_resume_port_tx
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4484 | 4547 | * @hw: pointer to the hardware structure
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