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Merge tag 'mailbox-v4.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar: - xgene: potential null pointer fix - omap: switch to spdx license and use of_device_get_match_data() to match data - ti-msgmgr: cleanup and optimisation. New TI specific feature - secure proxy thread. - mediatek: add driver for CMDQ controller. - nxp: add driver for MU controller * tag 'mailbox-v4.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: Add support for i.MX messaging unit dt-bindings: mailbox: imx-mu: add generic MU channel support dt-bindings: arm: fsl: add mu binding doc mailbox: add MODULE_LICENSE() for mtk-cmdq-mailbox.c mailbox: mediatek: Add Mediatek CMDQ driver dt-bindings: soc: Add documentation for the MediaTek GCE unit mailbox: ti-msgmgr: Add support for Secure Proxy dt-bindings: mailbox: Add support for secure proxy threads mailbox: ti-msgmgr: Move the memory region name to descriptor mailbox: ti-msgmgr: Change message count mask to be descriptor based mailbox: ti-msgmgr: Allocate Rx channel resources only on request mailbox: ti-msgmgr: Get rid of unused structure members mailbox/omap: use of_device_get_match_data() to get match data mailbox/omap: switch to SPDX license identifier mailbox: xgene-slimpro: Fix potential NULL pointer dereference
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‎Documentation/devicetree/bindings/mailbox/fsl,mu.txt

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NXP i.MX Messaging Unit (MU)
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--------------------------------------------------------------------
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The Messaging Unit module enables two processors within the SoC to
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communicate and coordinate by passing messages (e.g. data, status
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and control) through the MU interface. The MU also provides the ability
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for one processor to signal the other processor using interrupts.
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Because the MU manages the messaging between processors, the MU uses
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different clocks (from each side of the different peripheral buses).
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Therefore, the MU must synchronize the accesses from one side to the
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other. The MU accomplishes synchronization using two sets of matching
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registers (Processor A-facing, Processor B-facing).
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Messaging Unit Device Node:
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=============================
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Required properties:
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-------------------
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- compatible : should be "fsl,<chip>-mu", the supported chips include
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imx6sx, imx7s, imx8qxp, imx8qm.
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The "fsl,imx6sx-mu" compatible is seen as generic and should
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be included together with SoC specific compatible.
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- reg : Should contain the registers location and length
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- interrupts : Interrupt number. The interrupt specifier format depends
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on the interrupt controller parent.
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- #mbox-cells: Must be 2.
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<&phandle type channel>
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phandle : Label name of controller
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type : Channel type
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channel : Channel number
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This MU support 4 type of unidirectional channels, each type
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has 4 channels. A total of 16 channels. Following types are
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supported:
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0 - TX channel with 32bit transmit register and IRQ transmit
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acknowledgment support.
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1 - RX channel with 32bit receive register and IRQ support
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2 - TX doorbell channel. Without own register and no ACK support.
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3 - RX doorbell channel.
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Optional properties:
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-------------------
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- clocks : phandle to the input clock.
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- fsl,mu-side-b : Should be set for side B MU.
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Examples:
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--------
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lsio_mu0: mailbox@5d1b0000 {
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compatible = "fsl,imx8qxp-mu";
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reg = <0x0 0x5d1b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};

‎Documentation/devicetree/bindings/mailbox/mtk-gce.txt

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MediaTek GCE
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===============
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The Global Command Engine (GCE) is used to help read/write registers with
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critical time limitation, such as updating display configuration during the
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vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
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CMDQ driver uses mailbox framework for communication. Please refer to
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mailbox.txt for generic information about mailbox device-tree bindings.
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Required properties:
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- compatible: Must be "mediatek,mt8173-gce"
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- reg: Address range of the GCE unit
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- interrupts: The interrupt signal from the GCE block
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- clock: Clocks according to the common clock binding
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- clock-names: Must be "gce" to stand for GCE clock
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- #mbox-cells: Should be 3.
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<&phandle channel priority atomic_exec>
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phandle: Label name of a gce node.
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channel: Channel of mailbox. Be equal to the thread id of GCE.
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priority: Priority of GCE thread.
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atomic_exec: GCE processing continuous packets of commands in atomic
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way.
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Required properties for a client device:
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- mboxes: Client use mailbox to communicate with GCE, it should have this
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property and list of phandle, mailbox specifiers.
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- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
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to the register address.
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Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
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sub-system ids, thread priority, event ids.
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Example:
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gce: gce@10212000 {
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compatible = "mediatek,mt8173-gce";
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reg = <0 0x10212000 0 0x1000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_GCE>;
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clock-names = "gce";
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thread-num = CMDQ_THR_MAX_COUNT;
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#mbox-cells = <3>;
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};
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Example for a client device:
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mmsys: clock-controller@14000000 {
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compatible = "mediatek,mt8173-mmsys";
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mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
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<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
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mediatek,gce-subsys = <SUBSYS_1400XXXX>;
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mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
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CMDQ_EVENT_MUTEX1_STREAM_EOF>;
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...
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};

‎Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt

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Texas Instruments' Secure Proxy
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========================================
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The Texas Instruments' secure proxy is a mailbox controller that has
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configurable queues selectable at SoC(System on Chip) integration. The
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Message manager is broken up into different address regions that are
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called "threads" or "proxies" - each instance is unidirectional and is
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instantiated at SoC integration level by system controller to indicate
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receive or transmit path.
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Message Manager Device Node:
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===========================
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Required properties:
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--------------------
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- compatible: Shall be "ti,am654-secure-proxy"
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- reg-names target_data - Map the proxy data region
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rt - Map the realtime status region
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scfg - Map the configuration region
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- reg: Contains the register map per reg-names.
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- #mbox-cells Shall be 1 and shall refer to the transfer path
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called thread.
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- interrupt-names: Contains interrupt names matching the rx transfer path
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for a given SoC. Receive interrupts shall be of the
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format: "rx_<PID>".
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- interrupts: Contains the interrupt information corresponding to
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interrupt-names property.
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Example(AM654):
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------------
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secure_proxy: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x0 0x32c00000 0x0 0x100000>,
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<0x0 0x32400000 0x0 0x100000>,
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<0x0 0x32800000 0x0 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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dmsc: dmsc {
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[...]
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mbox-names = "rx", "tx";
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# RX Thread ID is 11
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# TX Thread ID is 13
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mboxes= <&secure_proxy 11>,
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<&secure_proxy 13>;
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[...]
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};

‎drivers/mailbox/Kconfig

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The controller has 3 mailbox channels, the last of which can be
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used in Secure mode only.
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config IMX_MBOX
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tristate "i.MX Mailbox"
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depends on ARCH_MXC || COMPILE_TEST
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help
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Mailbox implementation for i.MX Messaging Unit (MU).
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config PLATFORM_MHU
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tristate "Platform MHU Mailbox"
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depends on OF
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Mailbox implementation for STMicroelectonics STM32 family chips
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with hardware for Inter-Processor Communication Controller (IPCC)
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between processors. Say Y here if you want to have this support.
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config MTK_CMDQ_MBOX
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tristate "MediaTek CMDQ Mailbox Support"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select MTK_INFRACFG
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help
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Say yes here to add support for the MediaTek Command Queue (CMDQ)
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mailbox driver. The CMDQ is used to help read/write registers with
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critical time limitation, such as updating display configuration
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during the vblank.
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endif

‎drivers/mailbox/Makefile

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obj-$(CONFIG_ARM_MHU) += arm_mhu.o
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obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
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obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o
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obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
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obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o

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