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Mark yao
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drm/rockchip: vop: move write_relaxed flags to vop register
Since the drm atomic framework, only a small part of the vop register needs sync write, Currently seems only following registers need sync write: cfg_done, standby and interrupt related register. All ctrl registers are using the sync write method that is inefficient, hardcode the write_relaxed flags to vop registers, then can only do synchronize write for those actual needed register. Signed-off-by: Mark Yao <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Reviewed-by: Jeffy Chen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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+36
-35
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3 files changed

+36
-35
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‎drivers/gpu/drm/rockchip/rockchip_drm_vop.c

Lines changed: 11 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -42,33 +42,27 @@
4242
#include "rockchip_drm_psr.h"
4343
#include "rockchip_drm_vop.h"
4444

45-
#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
46-
vop_mask_write(x, off, mask, shift, v, write_mask, true)
47-
48-
#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
49-
vop_mask_write(x, off, mask, shift, v, write_mask, false)
50-
51-
#define REG_SET(x, base, reg, v, mode) \
52-
__REG_SET_##mode(x, base + reg.offset, \
53-
reg.mask, reg.shift, v, reg.write_mask)
54-
#define REG_SET_MASK(x, base, reg, mask, v, mode) \
55-
__REG_SET_##mode(x, base + reg.offset, \
56-
mask, reg.shift, v, reg.write_mask)
45+
#define REG_SET(x, base, reg, v) \
46+
vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
47+
v, reg.write_mask, reg.relaxed)
48+
#define REG_SET_MASK(x, base, reg, mask, v) \
49+
vop_mask_write(x, base + reg.offset, \
50+
mask, reg.shift, v, reg.write_mask, reg.relaxed)
5751

5852
#define VOP_WIN_SET(x, win, name, v) \
59-
REG_SET(x, win->base, win->phy->name, v, RELAXED)
53+
REG_SET(x, win->base, win->phy->name, v)
6054
#define VOP_SCL_SET(x, win, name, v) \
61-
REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
55+
REG_SET(x, win->base, win->phy->scl->name, v)
6256
#define VOP_SCL_SET_EXT(x, win, name, v) \
63-
REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
57+
REG_SET(x, win->base, win->phy->scl->ext->name, v)
6458
#define VOP_CTRL_SET(x, name, v) \
65-
REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
59+
REG_SET(x, 0, (x)->data->ctrl->name, v)
6660

6761
#define VOP_INTR_GET(vop, name) \
6862
vop_read_reg(vop, 0, &vop->data->ctrl->name)
6963

7064
#define VOP_INTR_SET(vop, name, mask, v) \
71-
REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
65+
REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v)
7266
#define VOP_INTR_SET_TYPE(vop, name, type, v) \
7367
do { \
7468
int i, reg = 0, mask = 0; \

‎drivers/gpu/drm/rockchip/rockchip_drm_vop.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ struct vop_reg {
2929
uint32_t shift;
3030
uint32_t mask;
3131
bool write_mask;
32+
bool relaxed;
3233
};
3334

3435
struct vop_ctrl {

‎drivers/gpu/drm/rockchip/rockchip_vop_reg.c

Lines changed: 24 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -20,17 +20,23 @@
2020
#include "rockchip_drm_vop.h"
2121
#include "rockchip_vop_reg.h"
2222

23-
#define VOP_REG(off, _mask, s) \
24-
{.offset = off, \
23+
#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
24+
{ \
25+
.offset = off, \
2526
.mask = _mask, \
26-
.shift = s, \
27-
.write_mask = false,}
27+
.shift = _shift, \
28+
.write_mask = _write_mask, \
29+
.relaxed = _relaxed, \
30+
}
2831

29-
#define VOP_REG_MASK(off, _mask, s) \
30-
{.offset = off, \
31-
.mask = _mask, \
32-
.shift = s, \
33-
.write_mask = true,}
32+
#define VOP_REG(off, _mask, _shift) \
33+
_VOP_REG(off, _mask, _shift, false, true)
34+
35+
#define VOP_REG_SYNC(off, _mask, _shift) \
36+
_VOP_REG(off, _mask, _shift, false, false)
37+
38+
#define VOP_REG_MASK_SYNC(off, _mask, _shift) \
39+
_VOP_REG(off, _mask, _shift, true, false)
3440

3541
static const uint32_t formats_win_full[] = {
3642
DRM_FORMAT_XRGB8888,
@@ -116,7 +122,7 @@ static const struct vop_intr rk3036_intr = {
116122
};
117123

118124
static const struct vop_ctrl rk3036_ctrl_data = {
119-
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
125+
.standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
120126
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
121127
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
122128
.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
@@ -125,7 +131,7 @@ static const struct vop_ctrl rk3036_ctrl_data = {
125131
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
126132
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
127133
.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
128-
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
134+
.cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
129135
};
130136

131137
static const struct vop_data rk3036_vop = {
@@ -201,7 +207,7 @@ static const struct vop_win_phy rk3288_win23_data = {
201207
};
202208

203209
static const struct vop_ctrl rk3288_ctrl_data = {
204-
.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
210+
.standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
205211
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
206212
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
207213
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
@@ -222,7 +228,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
222228
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
223229
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
224230
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
225-
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
231+
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
226232
};
227233

228234
/*
@@ -266,7 +272,7 @@ static const struct vop_data rk3288_vop = {
266272
};
267273

268274
static const struct vop_ctrl rk3399_ctrl_data = {
269-
.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
275+
.standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
270276
.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
271277
.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
272278
.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
@@ -290,7 +296,7 @@ static const struct vop_ctrl rk3399_ctrl_data = {
290296
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
291297
.line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
292298
.line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
293-
.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
299+
.cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
294300
};
295301

296302
static const int rk3399_vop_intrs[] = {
@@ -306,9 +312,9 @@ static const int rk3399_vop_intrs[] = {
306312
static const struct vop_intr rk3399_vop_intr = {
307313
.intrs = rk3399_vop_intrs,
308314
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
309-
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
310-
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
311-
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
315+
.status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0xffff, 0),
316+
.enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0xffff, 0),
317+
.clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0),
312318
};
313319

314320
static const struct vop_data rk3399_vop_big = {

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